A receiver circuit is disclosed. The receiver circuit includes an amplifier configured to generate an RF signal based on a received signal, where the RF signal includes an information signal and a blocker signal modulating an RF carrier frequency. The receiver circuit also includes an RF filter connected to the amplifier, where the RF filter is configured to selectively attenuate the blocker signal.

In electronic circuits having various gain states, small gain phase shift differences required among various gain states may pose a challenging problem. The disclosed methods and devices provide solution to such challenge. Electronic circuits are described wherein a first path including an amplifier may be bypassed by a second path including only passive elements and for gain states smaller than 0 dB. In such electronic circuits, a phase shifter included in the second path can be adjusted to address the required phase shift among various gain states.

A diode linearizer according to the present invention has parallelly mounting linearizer core units on a RF signal path via capacitors between the RF signal path and a ground, thus does not need a switch using an FET, for example, at a time of selectively operating a plurality of linearizer core units. Moreover, the diode linearizer does not need a capacitor in series for blocking a direct current between RF signal input and output terminals. Thus, a range of a gain which can be compensated by the diode linearizer can be increased. Furthermore, an insertion loss of the RF signal path in a state where the diode linearizer is off can be reduced, and a range of a gain expansion in operation can be increased. The switch is not used, or the number of elements of the capacitors which are needed is small, thus a circuit size is also small.

Examples disclosed herein relate to a high gain active relay antenna system. The active relay antenna system comprises a first antenna pair having a first receive antenna and a first transmit antenna to communicate wireless signals in a forward link from a base station to a plurality of users; and a second antenna pair having a second receive antenna and a second transmit antenna to communicate wireless signals in a return link from the plurality of users to the base station. The active relay antenna system further comprises a first active relay section and a second active relay section to provide for adjustable power gain in the wireless signals.

Embodiments of the disclosure generally relate to a multi-channel Doherty power amplifier, a multi-antenna transmitter, and a method for turning on the multi-channel Doherty amplifier. The multi-channel Doherty power amplifier includes: multiple input ports and the same number of output ports corresponding to multiple channels, the multiple channels having the same characteristics for radio signal amplification and transmission; multiple private peaking amplifiers corresponding to the multiple channels; and a common Doherty core shared by the multiple private peaking amplifiers. The multiple private peaking amplifiers and the common Doherty core are configured to amplify identical multi-channel signal for multiple inputs and multiple outputs, thus higher saving ratio and better channel performance (output power, linearity, efficiency, power gain etc.) consistency would be greatly improved.

A power amplifier including a cascode output stage, a bias circuit, and a temperature compensation and bias boost circuit. The cascode output stage has an input and an output and includes first and second transistors connected in series. A base of the first transistor is coupled to the input, an emitter of the first transistor is coupled to a reference potential, a collector of the first transistor is coupled to an emitter of the second transistor, and a collector of the second transistor is coupled to a supply voltage and the output. The bias circuit is coupled to the base of the second transistor. The bias boost circuit is coupled to the base of the first transistor, compensates for changes in temperature of the cascode output stage, and increases a bias current provided to the first transistor responsive to an increase in the temperature of the cascode output stage.

An multistage amplifier includes first to third FETs, a drain of the second FET is connected to a gate of the third FET in an AC manner, a source thereof is grounded in a DC manner, a drain of the first FET is connected to a gate of the second FET in an AC manner, a source thereof is grounded in a DC manner, a gate thereof receives a high frequency signal, a drain of the third FET receives a bias current and outputs an amplified signal, a source thereof is grounded in an AC manner, the drains of the first and second FETs are connected to the source of the third FET in a DC manner via a transmission line having an electrical length of /4 when a wavelength of the high frequency signal is , and a size of third FET is greater than other FETs.

Example signal processing apparatus and signal processing methods are described. One example signal processing apparatus includes a signal matching circuit, a first signal processing branch, and a second signal processing branch. An output end of the signal matching circuit is separately coupled to an input end of the first signal processing branch and an input end of the second signal processing branch, and an output end of the first signal processing branch is coupled to the input end of the second signal processing branch.

A filter includes M filter circuits. The M filter circuits are sequentially cascaded from an input terminal to an output terminal, in order to generate an output signal according to an input signal, in which M is a positive integer greater than or equal to 2. The M filter circuits include at least one first filter circuit and at least one second filter circuit. Each of the at least one first filter circuit is set to be an active filter circuit, and each of the at least one second filter circuit is set to be a passive filter circuit.

The present disclosure provides an amplifier circuit that includes one or more amplifier stages, each of the one or more amplifier stages including a complementary transistor configuration. The complementary transistor configuration includes an NMOS transistor and a PMOS transistor. The NMOS transistor is electrically coupled in parallel to the PMOS transistor. The amplifier circuit further includes an output amplifier stage electrically coupled to an output of the one or more amplifier stages, the output amplifier stage including a non-complementary transistor configuration including one or more NMOS transistors or PMOS transistors.