Examples disclosed herein relate to a high gain active relay antenna system. The active relay antenna system comprises a first antenna pair having a first receive antenna and a first transmit antenna to communicate wireless signals in a forward link from a base station to a plurality of users; and a second antenna pair having a second receive antenna and a second transmit antenna to communicate wireless signals in a return link from the plurality of users to the base station. The active relay antenna system further comprises a first active relay section and a second active relay section to provide for adjustable power gain in the wireless signals.

A power amplifier circuit includes an amplifier unit disposed on a die of a semiconductor device. The amplifier unit includes an amplifier transistor. The power amplifier circuit further includes a detector transistor disposed on the die of the semiconductor device, a variable attenuator that compensates for a gain of the amplifier unit, a bias level setting holding unit that holds a bias level setting value, which is set based on at least a detection value of the detector transistor, and a bias generation unit that generates a bias value of the variable attenuator based on the bias level setting value.

Modern modulator drivers must be capable of delivering a large output voltage into a tens of ohms modulator, while minimizing the amount of distortion added by the driver. The driver should deliver the output voltage without exceeding a maximum distortion while minimizing the DC power consumption. Accordingly, a modulator driver includes a final stage amplifier with auxiliary transistors that turn on when the conventional differential pair of transistors approaches their maximum voltage of the linear region of their transfer function, thereby providing a more linear transfer function, in particular at large input voltages.

A communication circuit, including a first supply modulator configured to provide a first supply voltage; a first power amplifier configured to generate a first output signal by amplifying a first input signal corresponding to a first operation frequency band, a second power amplifier configured to generate a second output signal by amplifying a second input signal corresponding to a second operation frequency band; and a switching circuit configured to selectively provide the first supply voltage from the first supply modulator to the second power amplifier based on a first switching signal according to an operation node.

A first transmission line and a second transmission line that are connected in series to each other are disposed at different positions in a thickness direction of a substrate. A third transmission line is disposed between the first transmission line and the second transmission line in the thickness direction of the substrate. The third transmission line includes a first end portion connected to one end portion of the first transmission line, and a second end portion that is AC-grounded. The first transmission line and the second transmission line are electromagnetically coupled to the third transmission line.

A radio frequency amplifier circuit is provided. A matching circuit is configured on a radio frequency path of an input end or an output end of an amplifier. An inductance-capacitance resonance circuit and the matching circuit share an inductor included in the matching circuit to generate a corresponding resonance frequency. The matching circuit provides an input impedance or an output impedance matching two fundamental tones in a radio frequency signal at a first frequency and a second frequency. The inductance-capacitance resonance circuit provides a filtering path for filtering a signal component outside a frequency band formed by the first frequency and the second frequency in the radio frequency signal.

Within a modulator driver, different blocks are employed, e.g. a buffer, one or more variable gain amplifiers (VGA), and a final driver stage. Each of these blocks has an optimum bias point for best performance; however, interconnecting the blocks requires sharing the DC bias points in their interface, which does not necessarily match the optimum performance bias point of each block. Accordingly, a first offset feedback loop extending from reference points after a selected one of the blocks to an input of one of the blocks. The first offset feedback loop includes current sources capable of delivering a variable current to the input of the selected block in order to compensate any offset in an amplified differential input electrical signal measured at the reference points. A first bias feedback loop is also provided, including a current sinker for subtracting excess current introduced in the first offset compensation feedback loop.

An input circuit includes an input stage having an input node and a direct-current (DC) amplifier coupled to the input node. The input circuit also includes an alternating-current (AC) amplifier coupled to an output node of the DC amplifier. The input circuit also includes a capacitor coupled between the input node and the output node of the DC amplifier. The input circuit also includes a voltage divider coupled to the DC amplifier and the AC amplifier. The voltage divider includes first resistor associated with the DC amplifier and a second resistor associated with the AC amplifier, where the first resistor is larger than the second resistor.

Provided is an amplification circuit for amplifying an input signal. The amplification circuit includes an input stage including an input matching circuit that receives the input signal and an input attenuation circuit that attenuates a gain for the input signal outside an operating frequency band of the amplification circuit, a transistor that amplifies the input signal provided from the input stage, and an output stage including an output matching circuit that receives a signal amplified by the transistor and an output attenuation circuit that attenuates the gain for the input signal outside the operating frequency band of the amplification circuit, and the input attenuation circuit includes a first resistor and a second resistor that are connected to a ground voltage, a first passive element connected between the input matching circuit and the second resistor, and a second passive element connected between the first passive element and the first resistor.

A signal processing circuit reduces die size and power consumption for each antenna element. The signal processing circuit includes a first set of ports, a third port, a first path, a second path and a first transistor. The first path is between a first port of the first set of ports and the third port. The second path is between a second port of the first set of ports and the third port. The first transistor is coupled between the first path and the second path. The first transistor is configured to receive a control signal to control the first transistor to adjust an impedance between the first path and the second path.