A radio frequency (RF) transistor includes a drain, a source, and a gate. A first dielectric having a first dielectric constant is over the source and the drain. A gap is in the first dielectric and over the gate, the gap extending to the gate. A second dielectric is situated in the gap. The second dielectric has a second dielectric constant substantially less than the first dielectric constant so as to reduce a C.sub.OFF of the RF transistor. The RF transistor can be part of a stack of RF transistors in an RF switch. The RF switch can be situated between an antenna and an amplifier.

An electronic device is provided The electronic device includes a patch antenna element, at least one antenna including a first feeding unit electrically connected to the patch antenna element and a second feeding unit electrically connected to the patch antenna element so as to have a designated isolation for a signal that is input to the first feeding unit, a radio frequency integrated circuit (RFIC) which includes a first communication circuit including a first transmission circuit and a first reception circuit which are electrically connected to the first feeding unit, and a second communication circuit including a second transmission circuit and a second reception circuit which are electrically connected to the second feeding unit, and a processor.

A receiver front end having low noise amplifiers (LNAs) is disclosed herein. A cascode having a common source configured input FET and a common gate configured output FET can be turned on or off using the gate of the output FET. A first switch is provided that allows a connection to be either established or broken between the source terminal of the input FET of each LNA. A drain switch is provided between the drain terminals of input FETs to place the input FETs in parallel. This increases the g m of the input stage of the amplifier, thus improving the noise figure of the amplifier.

Resistor mismatch may be digitally compensated based on a known resistor mismatch, power supply information, and/or other operating parameters of the amplifier. The digital compensation may be applied to the digital input signal before conversion for processing and amplification in the analog domain. An amplifier with digital compensation for resistor mismatch may be used in a class-D amplifier with a closed loop and feedforward feedback. A class-D or other amplifier with digital compensation may be integrated with electronic devices such as mobile phones.

A multimode envelope tracking (ET) circuit and related apparatus is provided. The multimode ET circuit is configured to provide an ET voltage(s) to an amplifier circuit(s) for amplifying a radio frequency (RF) signal(s) that may correspond to a wider range of modulation bandwidth. In this regard, the multimode ET circuit is configured to switch dynamically and opportunistically between different operation modes based on the modulation bandwidth of the RF signal(s). In examples discussed herein, the multimode ET circuit is configured to support a single amplifier circuit in a high-modulation-bandwidth mode and an additional amplifier circuit(s) in a mid-modulation-bandwidth mode and a low-modulation-bandwidth mode. By switching dynamically and opportunistically between different operation modes, it may be possible to reduce undesired series resonance that may cause distortion in the ET voltage(s), thus helping to improve efficiency and performance of the amplifier circuit(s) supported by the multimode ET circuit.

An audio processing circuit includes a cascade operational amplifier circuit, an output node, and a pull-down circuit. The cascade operational amplifier circuit includes a first operational amplifier circuit and a second operational amplifier circuit. The first operational amplifier circuit includes a main operational amplifier and a secondary operational amplifier that are connected in parallel. The pull-down circuit is configured to pull down a voltage at the output node after the first operational amplifier circuit is turned on. The second operational amplifier circuit is configured to, after the secondary operational amplifier is turned on, control a voltage gain of the secondary operational amplifier to change gradually from low to high.

A six phase capacitively coupled chopper amplifier. Two phases provide a zeroing phase to zero the feedback capacitors and set the input common mode value. Two phases provide a passive transfer of an input charge from the input capacitors to the zeroed feedback capacitors. The final two phases are chopping and amplification phases. The zeroing phases address the input common mode without the need for biasing resistors. The passive transfer phases resolve the glitching that occurs if the feedback capacitors have to be recharged on each cycle of the chopping clock. Resolving the glitching and the charge time allows the frequency of the amplifier to increase.

A chopper-stabilized amplifier includes a first transconductance amplifier and a first chopper circuit coupled to an input of the first transconductance amplifier. A second chopper circuit is coupled to an output of the first transconductance amplifier. The chopper-stabilized amplifier also includes second and third transconductance amplifiers having inputs coupled to the output of the first transconductance amplifier. The second transconductance amplifier produces an output responsive to a first notch clock signal having a first phase relative to the chopping of the second chopper circuit. The third transconductance amplifier produces an output responsive to a second notch clock signal having a second phase relative to the first phase. The output signals produced by the second and third transconductance amplifiers are added to filter ripple noise at the outputs of the second and third transconductance amplifiers.

A linear amplifier is provided to have higher efficiency for an envelope tracking modulator. In one embodiment, a first stage amplifier circuit can be simply operated in a high gain mode or a high bandwidth mode for different applications, without using large chip area. In another embodiment, an output stage has a cascode structure whose dynamic range is controlled according to a voltage level of a supply voltage, to make a core device within the output stage have better protection and suitable dynamic range.

Circuits, devices and methods are disclosed, including radio-frequency circuitry comprising a polar modulator configured to invert a sampled transmitted signal into an inverted sampled transmitted signal, a signal combiner configured to combine the inverted sampled transmitted signal with a received signal and a control logic circuit coupled to the polar modulator, the control logic circuit configured to adjust one or more tuning parameters of the polar modulator for inverting the sampled transmitted signal.