A vector modulator includes a quadrature component generator, configured to generate an input in-phase signal and an input quadrature signal according to an input radio frequency (RF) signal; a switching circuit, receiving a plurality of bits, comprising a plurality of switches controlled by the plurality of bits, configured to generate an output in-phase signal and an output quadrature signal according to the plurality of bits, where the output in-phase signal and the output quadrature signal are related to input in-phase signal and the input quadrature signal; and a combining module, configured to generate an output RF signal according to the output in-phase signal and the output quadrature signal.

Charging and discharging circuits for assisting charge pumps are disclosed. In certain embodiments, a radio frequency (RF) switch system includes an RF switch that receives an RF signal and is controlled by a switch control signal received at an input, a first charge pump configured to generate a first charge pump voltage, a level shifter powered by the first charge pump voltage and that generates the switch control signal based on a switch enable signal, and a charge pump assistance switch coupled to the input of the radio frequency switch and that activates to assist the first charge pump in response to a transition of the switch enable signal from a first state to a second state.

Various aspects described herein relate to low-loss multi-band multiplexing schemes for a wireless communications system, for example, a 5th Generation (5G) New Radio (NR) system. In an aspect, a multiplexer for multi-band wireless communications comprises at least one tuning component configured to transmit or receive at least one signal within a frequency band that is selected from a plurality of frequency bands. The multiplexer further comprises at least one combining component, communicatively coupled with the at least one tuning component, configured to transmit or receive the at least one signal within the selected frequency band. In an aspect, the at least one tuning component is integrated on a chip and the at least one combining component is not integrated on the chip.

An output driver with programmable single-ended and differential outputs includes a first switch, a first output attenuator, and a programmable attenuator. The first switch is coupled in a shunt configuration to a first path of a differential output of a first amplifier. The first output attenuator is included in the first path and is coupled to the first switch in accordance with the shunt configuration. The programmable attenuator is included in a second path of the differential output of the first amplifier.

A dynamic amplifier with a bypass design. An input pair of transistors receives a pair of differential inputs Vip and Vin and further provides first, second and third terminals. A load circuit provides a pair of differential outputs Vop and Von with the load circuit connected at a common mode terminal. In an amplification phase, a driver for amplification is coupled to the first terminal and the load circuit is coupled to the second and third terminals. A bypassing circuit is specifically provided. The bypassing circuit is coupled to the second and third terminals during a bypass period within the amplification phase.

Aspects of this disclosure relate to compensating for dynamic error vector magnitude. A compensation circuit can generate a compensation signal based at least partly on an amount of time that an amplifier, such as a power amplifier, is turned off between successive transmission bursts of the amplifier. For example, the compensation circuit can charge a capacitor based at least partly on an amount of time that the amplifier is turned off between successive transmission bursts and generate the compensation signal based at least partly on an amount of charge stored on the capacitor. A bias circuit can receive the compensation signal, generate a bias signal based at least partly on the compensation signal, and provide the bias signal to the amplifier to bias the amplifier.

An amplifier amplifies an input signal. A splitter branches an output signal of the amplifier into a first signal path and a second signal path and performs impedance conversion of the first and second signal paths. A first output terminal outputs the output signal of the amplifier or a signal obtained by branching the output signal of the amplifier into the first signal path by the splitter. A second output terminal outputs the output signal of the amplifier or a signal obtained by branching the output signal of the amplifier into the second signal path by the splitter. An output controller switches whether the output signal of the amplifier is output from the first output terminal, is output from the second output terminal, or is branched by the splitter to be output from both the first and second output terminals.

Exemplary embodiments including an amplifier circuit that includes a radio-frequency (RF) amplifier comprising an input terminal and an output terminal, the RF amplifier being configured to amplify, across a wideband frequency range, an RF signal applied to the input terminal to generate an amplified RF signal at the output terminal. The amplifier circuit also includes a first impedance matching network connected to the RF amplifier output terminal. The first impedance matching network includes a first reactive circuit, having substantially fixed impedance, connected between the RF amplifier input terminal and ground; a second reactive circuit; and a switching device configured to couple the second reactive circuit to the first reactive circuit in an ON state, and to decouple the second reactive circuit from the first reactive circuit in an OFF state. In some embodiments, the amplifier circuit can include a second impedance matching network connected to the RF amplifier input terminal.

A receiver front end having low noise amplifiers (LNAs) is disclosed herein. A cascode having a common source configured input FET and a common gate configured output FET can be turned on or off using the gate of the output FET. A first switch is provided that allows a connection to be either established or broken between the source terminal of the input FET of each LNA. A drain switch is provided between the drain terminals of input FETs to place the input FETs in parallel. This increases the g.sub.m of the input stage of the amplifier, thus improving the noise figure of the amplifier.

A receiver front end having low noise amplifiers (LNAs) is disclosed herein. A cascode having a common source configured input FET and a common gate configured output FET can be turned on or off using the gate of the output FET. A first switch is provided that allows a connection to be either established or broken between the source terminal of the input FET of each LNA. A drain switch is provided between the drain terminals of input FETs to place the input FETs in parallel. This increases the g.sub.m of the input stage of the amplifier, thus improving the noise figure of the amplifier.