A multi-mode envelope tracking (ET) amplifier circuit is provided. The multi-mode ET amplifier circuit can operate in a low-resource block (RB) mode, a mid-RB mode, and a high-RB mode. The multi-mode ET amplifier circuit includes fast switcher circuitry having a first switcher path and a second switcher path and configured to generate an alternating current (AC) current. A control circuit activates the fast switcher circuitry in the mid-RB mode and the high-RB mode, while deactivating the fast switcher circuitry in the low-RB mode. More specifically, the control circuit selectively activates one of the first switcher path and the second switcher path in the mid-RB mode and activates both the first switcher path and the second switcher path in the high-RB mode. As a result, it is possible to improve efficiency of ET tracker circuitry and the multi-mode ET amplifier circuit in all operation modes.

High-performance radio frequency analog-to-digital converters (RF ADCs) demand high bandwidth, high linearity, and low noise input amplifiers. A Class-AB amplifier, including common-gate transistor devices and common-source transistor devices operating in parallel, offers high bandwidth and high linearity, while offering lower power operation when compared to Class-A amplifiers. The Class-AB amplifier can be followed by a Class-AB unity gain buffer comprising common-source transistor devices to provide additional isolation for the RF ADC from the circuitry preceding the Class-AB amplifier.

The present invention provides a voltage regulator including a voltage control circuit and a current control circuit. The voltage control circuit is configured to receive an output voltage of the voltage regulator to generate a first current to an output terminal of the voltage regulator; and the current control circuit is configured to generate a second current to the output terminal of the voltage regulator according to an output current of the voltage regulator, wherein the output current is generated according to the first current and the second current.

A signal processing system includes n paths of load modulation modules and a combination module, where then paths of load modulation modules are connected in parallel, an output end of each path of load modulation module is connected to an input end of the combination module, and n is an integer greater than 1; the n paths of load modulation modules include one path of main power amplification module and (n-1) paths of auxiliary power amplification modules, and the auxiliary power amplification modules are turned on when power values of signals received by input ends of the load modulation modules are greater than a first threshold; and the main power amplification module includes two outphasing power amplification units, and each path of auxiliary power amplification module includes two outphasing power amplifier arrays or one digital polar power amplifier array.

An embodiment of a Doherty amplifier includes a module substrate, first and second surface-mount devices coupled to a top surface of the module substrate, and an impedance inverter line assembly. The first and second surface-mount devices include first and second amplifier dies, respectively. The impedance inverter line assembly is electrically connected between outputs of the first and second amplifier dies. The impedance inverter line assembly includes an impedance inverter line coupled to the module substrate, a first lead of the first surface-mount device coupled between the first amplifier die output and a proximal end of the impedance inverter line, and a second lead of the second surface-mount device coupled between the second amplifier die output and a distal end of the impedance inverter line. According to a further embodiment, the impedance inverter line assembly has a 90 degree electrical length at a fundamental operational frequency of the Doherty amplifier.

This application relates to Class D amplifier circuits. A modulator controls a Class D output stage based on a modulator input signal (Dm) to generate an output signal (Vout) which is representative of an input signal (Din). An error block, which may comprise an ADC, generates an error signal (ε) from the output signal and the input signal. In various embodiments the extent to which the error signal (ε) contributes to the modulator input signal (Dm) is variable based on an indication of the amplitude of the input signal (Din). The error signal may be received at a first input of a signal selector block. The input signal may be received at a second input of the signal selector block. The signal selector block may be operable in first and second modes of operation, wherein in the first mode the modulator input signal is based at least in part on the error signal; and in the second mode the modulator input signal is based on the digital input signal and is independent of the error signal. The error signal can be used to reduce distortion at high signal levels but is not used at low signal levels and so the noise floor at low signal levels does not depend on the component of the error block.

A Doherty amplifier module includes a substrate, an RF signal splitter, a carrier amplifier die, and first and second peaking amplifier dies. The RF signal splitter divides an input RF signal into first, second, and third input RF signals, and conveys the input RF signals to splitter output terminals. The carrier amplifier die includes one or more first power transistors configured to amplify, along a carrier signal path, the first input RF signal to produce an amplified first RF signal. The peaking amplifier dies each include one or more additional power transistors configured to amplify, along first and second peaking signal paths, the second and third input RF signals to produce amplified second and third RF signals. The dies are coupled to the substrate so that the RF signal paths through the carrier and one or more of the peaking amplifier dies extend in substantially different (e.g., orthogonal) directions.

A second main electrode of a first transistor is connected to a first main electrode of a sixth transistor, a second main electrode of the sixth transistor is connected to a first main electrode of a fifth transistor at a first node, a second main electrode of the fifth transistor is connected to a second main electrode of a second transistor, a control electrode of the fifth transistor is connected to the second main electrode of the fifth transistor, a second main electrode of a third transistor is connected to a first main electrode of a fourth transistor at a second node, and a control electrode of the fourth transistor is connected to the control electrode of the fifth transistor. A gain control amplifier controls a voltage supplied to a control electrode of the sixth transistor such that the first node and the second node are equal in voltage.

A supply modulator is provided, having a first amplifier circuit configured to generate a first electrical signal, a second amplifier circuit configured to generate a second electrical signal, the first and second electrical signals being for driving an electrical load, and a control circuit electrically coupled to the first and second amplifier circuits wherein the control circuit is configured to generate a pulsed electrical signal and to supply an output control signal to the second amplifier circuit for controlling generation of the second electrical output signal, wherein the supply modulator is configured to operate in two modes of operation, for the first amplifier circuit to generate the first electrical signals in response to quiescent current of the first amplifier circuit, for the control circuit to generate a modulated electrical signal in accordance with a clock signal in one mode, and, for the second amplifier circuit to operate at different frequencies.

To easily adjust a gain of an amplifier. An applied input signal is input to a gate terminal of a first transistor, and a current depending on the applied input signal flows through the first transistor. A load section is connected to a drain terminal of the first transistor. A gate terminal of a second transistor is connected to the load section, and a current depending on a change in a voltage of the drain terminal of the first transistor flows through the second transistor. A source terminal of the first transistor and a drain terminal of the second transistor are connected in common to a first resistance, and the current from the first transistor and the current from the second transistor flow through the first resistance. A third transistor supplies a current approximately equal to the current of the second transistor. The current supplied by the third transistor is output from an output end.