Patent classifications
H03F2200/435
Peak detector and operational amplifier circuit therein
A peak detector utilizes two choppers to cancel offset voltage of a transconductance amplifier, so the influence of the offset voltage is preventable and the peak detection accuracy of the peak detector can be improved significantly.
AMPLIFICATION CIRCUIT WITH READ/WRITE CIRCUIT
The invention relates to an amplification circuit (100), comprising: a VGA (2), an AGC loop (10) for automatically controlling the gain of the VGA (2), a switching circuit (14) for switching between an AGC mode, in which the gain of the VGA (2) is automatically controlled by an output signal of the AGC loop (10) and a manual gain control, MGC, mode, in which the gain of the VGA (2) can be manually controlled by an input signal, and a read/write circuit (30) with a contact (31) for connection to a peripheral system, wherein the read/write circuit (30) is configured, in the MGC mode, to provide the input signal from the contact (31) via a write-mode path (32) to the VGA (2), and, in the AGC mode, to provide the output signal of the AGC loop (10) via a read-mode path (33) on the contact (31).
System for monitoring the peak power for an RF power amplification and associated method of calculating peak value and of selecting supply voltage
Disclosed is a system for monitoring the peak power of a telecommunication signal to be transmitted for RF power amplification of the telecommunication signal to be transmitted, including a digital processing device, a digital to RF converter and a dc-dc converter, wherein the output of the dc-dc converter can take a discrete voltage value from N discrete voltage values, N being an integer equal to or greater than 2, the digital processing device including a processing path including an envelope tracking control logic adapted to create a continuous envelope tracking control signal. The processing path further includes logic for driving the dc-dc converter including a peak value calculating device and a power supply voltage selecting device.
Power amplifier with supply switching
A power amplifier with supply switching is provided. The power amplifier detects a magnitude of an outgoing broadband communication signal and determines whether the magnitude exceeds a predetermined voltage threshold. The power amplifier applies a first gain to the outgoing broadband communication signal using a first voltage supply rail when it is determined that the magnitude exceeds the predetermined voltage threshold and a second gain using a second voltage supply rail that is smaller than the first voltage supply rail when it is determined that the magnitude does not exceed the predetermined voltage threshold. The power amplifier produces an output signal from the outgoing broadband communication signal with the applied first gain or the applied second gain, wherein a current of the outgoing broadband communication signal is switched between the first voltage supply rail and the second voltage supply rail in response to the magnitude being detected.
Wideband adaptive bias circuits for power amplifiers
Methods and apparatus for providing adaptive biasing to power amplifiers. Adaptive bias circuits are configured to provide sharp turn on and/or current clamping to improve the efficiency of a power amplifier over a wide input signal bandwidth. Sharp turn on may be achieved using a subtraction technique to subtract outputs from multiple detectors. Clamping may be achieved using MOSFET device characteristics to pull the device from the triode region into the saturation, subtraction techniques to subtract the outputs from multiple detectors, and/or by using circuit devices, such as diodes.
OPTICAL RECEIVER
A receiver has a differential transimpedance amplifier (4) with two inputs and two outputs. The differential transimpedance amplifier (4) provides a differential output and this is peak-detected (15, 16) to provide amplitude reference signals. The differential transimpedance amplifier output and the amplitude reference signals are fed to a differential summing amplifier (10), which provides a fully differential signal to a comparator, or to an automatic gain control circuit (5) to regulate the differential transimpedance amplifier gain. The differential summing amplifier (10) output is a fully differential signal, thereby having lower distortion for DC and burst mode receiver applications.
DIGITAL DYNAMIC BIAS CIRCUIT
Circuits and methods for reducing the cost and/or power consumption of a user terminal and/or the gateway of a telecommunications system (550) that may include a telecommunications satellite. Embodiments generate a dynamic input bias signal based upon an information signal envelope (which may be pre-distorted) which is applied to the signal input of a power amplifier (PA), thus reducing average power consumption. Other embodiments further include dynamic linearization (518) of the information signal, and/or variation of the supply voltage to the power amplifier (PA) as a function of the envelope of the information signal. Another aspect is a multi-stage chained feedback regulated voltage supply circuit for providing two or more output voltages that may be used as alternative supply voltages to a power amplifier (PA).
Power amplifier system and associated control circuit and control method
A control circuit of a power amplifier includes a peak detector, a first comparator, a first current source, a second comparator, a second current source and a bias circuit. The peak detector is arranged for detecting an amplitude of an input signal. The first comparator is arranged for comparing the amplitude of the input signal with a first threshold to generate a first comparing result. The first current source is arranged for generating a first current according to the first comparing result The second comparator is arranged for comparing the amplitude of the input signal with a second threshold to generate a second comparing result. The second current source is arranged for generating a second current according to the second comparing result. The bias circuit is arranged for generating a bias voltage according to the first current and the second current to the power amplifier.
RECEIVER CIRCUIT
A receiver circuit, comprising: an receiver-input-terminal configured to receive input-signalling; an receiver-output-terminal configured to provide output-signalling; a plurality of sub-receivers, each configured to compare the received input-signalling with a different effective threshold value in order to provide a digital sub-receiver-output-signal, wherein the different effective threshold values have weighted values in a sequence between a least significant value and a most significant value; a controller configured to, in response to detecting calibration-signalling at the receiver-input-terminal: process the digital sub-receiver-output-signals in order to identify the sub-receiver with the most significant effective threshold value that is triggered by the calibration-signalling as a triggered-sub-receiver; identify a preceding-sub-receiver as the sub-receiver that has an effective threshold value that is before that of the triggered-sub-receiver in the sequence of weighted effective threshold values; and configure the receiver circuit such that, for subsequent signal processing, the sub-receiver-output-signal from the preceding-sub-receiver is provided to the receiver-output-terminal.
Amplifier system, controller of main amplifier and associated control method
The present invention provides a control circuit to stabilize an output power of a power amplifier. The control circuit comprises a voltage clamping loop, a current clamping loop and a loop for reducing power variation under VSWR, where the voltage clamping loop is used to clamp an output voltage of the power amplifier within a defined voltage range, the current clamping loop is used to clamp a current of the power amplifier within a defined current range, and the loop for reducing power variation under VSWR is implemented by an impedance detector to compensate the output power under VSWR variation.