Methods and devices are described for compensating an effect of aging due to, for example, hot carrier injection, or other device degradation mechanisms affecting a current flow, in an RF amplifier. In one case a replica circuit is used to sense the aging of the RF amplifier and adjust a biasing of the RF amplifier accordingly.

A device includes a variable gain amplifier, a voltage shifter, a variable gain amplifier half replica module, and an analog to digital converter. The variable gain amplifier includes an input terminal to receive an input signal, an output terminal to provide a first output signal that is biased based on a first common-mode voltage reference. The voltage shifter circuit includes first and second input terminals, and an output terminal to provide, to the analog to digital converter, a third output signal that is biased based on a second common-mode voltage reference. The variable gain amplifier half replica module includes an output terminal coupled to the second input terminal of the voltage shifter circuit, the variable gain amplifier half replica module to control the third output signal of the voltage shifter circuit based on the first common-mode voltage reference and the second common-mode voltage reference.

A sense amplifier circuit comprising a first-, second-, third- and fourth-amplification-blocks, each amplification-block comprising: an amplification-block-transistor comprising and an amplification-block-resistor. The amplification-block-transistor includes: a first-conduction-channel-terminal, a second-conduction-channel-terminal that is connected to an amplification-block-output-node, and a control-terminal that is connected to an amplification-block-control-node. The sense amplifier circuit also comprises: an amplification-block-resistor connected in series between an amplification-block-input-node and the first-conduction-channel-terminal; a first-bias-voltage-source connected to the amplification-block-control-nodes of the first- and third-amplification-blocks, a second-bias-voltage-source connected to the amplification-block-control-nodes of the second- and fourth-amplification-blocks. The sense amplifier circuit also comprises: a first-common-mode-voltage-resistor connected in series between a first-sensed-output-terminal and a common-mode-voltage-node; and a second-common-mode-voltage-resistor connected in series between a second-sensed-output-terminal and the common-mode-voltage-node.

Disclosed embodiments include a method for reducing amplifier offset drift comprised of receiving a first differential input signal at a first transistor base terminal and a second differential input signal at a second transistor base terminal, coupling the collector of the first transistor to the emitter of a third transistor and the emitter of the second transistor to the emitter of a fourth transistor, then coupling the base of the third transistor to the base of the fourth transistor. The method is also comprised of coupling the collector of the fourth transistor to an output terminal, generating a temperature dependent error correction current to minimize the difference in the amount of current flowing through the third transistor and the amount of current flowing through the fourth transistor, then injecting the error correction current into the emitter terminal of at least one of either the third transistor or the fourth transistor.

A pipelined SAR ADC includes a first stage and passive residue transfer is used to boost a conversion speed. Owing to the passive residue transfer, the first stage may be released during a residue amplification phase, cutting down a large part of the first-stage timing budget. An asynchronous timing scheme may also be adopted in both the first- and second-stage SAR ADCs to maximize the overall conversion speed. Lastly, a dynamic amplifier with proposed PVT stabilization technique may be employed to further save power consumption and improve the conversion speed simultaneously.

At least one method, apparatus and system disclosed involves providing semiconductor device having transistors comprising back gates and front gates. The semiconductor device comprises a signal processing unit for processing an input signal to provide an output signal. The signal processing unit includes a first transistor and a second transistor. The first transistor includes a first back gate electrically coupled to a first front gate. The signal processing unit also includes a second transistor operatively coupled to the first transistor. The second transistor includes a second back gate electrically coupled to a second front gate. The semiconductor device also includes a gain circuit for providing a gain upon the output signal. The semiconductor device also includes a bias circuit to provide a first bias signal to the first back gate and a second bias signal to the second back gate.

Certain aspects of the present disclosure provide an amplification system. The amplification system generally includes: a first amplifier having an output coupled to an output of the amplification system; a second amplifier, inputs of the first amplifier and the second amplifier being coupled to an input of the amplification system; an impedance coupled to an output of the second amplifier; and a biasing circuit having a first voltage sense input coupled to the output of the first amplifier, a second voltage sense input coupled to the output of the second amplifier, and an output coupled to a bias input of the first amplifier.

Radio Frequency (RF) amplifier design with RFIC suffers gain variations from gain variations due to wafer process variations, temperature changes, and supply voltage changes. Three methods are proposed to achieve constant amplifier gain, either through on-chip wafer calibration, or self-calibration. Through automatic adjustment of amplifier bias current, the proposed methods maintain constant amplifier gain over process, temperature, supply voltage variations. Under the proposed Method 1, a constant transconductance Gm with enhanced gain accuracy is maintained via wafer calibration. Under the proposed Method 2, a constant transconductance Gm is maintained by time-domain averaging through different transistors. Under the proposed Method 3, a constant Gm*R or RF gain is maintained considering the impedance of a matching network of the RF amplifier.

The present disclosure relates to a radio frequency power amplifier system (200) comprising a first (114) and a second input port (121). The radio frequency power amplifier system (200) comprises a main amplifier (101) having an input (107) and an output (108) and a first (102) and a second auxiliary amplifier (122) having respective inputs (109, 129) and outputs (110, 128). The radio frequency power amplifier system (200) comprises an internal load (103) connected to the output (110) of the first auxiliary amplifier (102), a feedback network (104) having an input end (111) connected to the output (110) of the first auxiliary amplifier (102) and an output end (112) connected to the input (109) of the first auxiliary amplifier (102). The radio frequency power amplifier system (200) also comprises a feedforward amplifier (123) having an input (124) and an output (130). The inputs (107, 129, 109) of the main amplifier and the auxiliary amplifiers are interconnected with the first input port (114) at a common input node (113), the output (128) of the second auxiliary amplifier (122) and the second input port (121) are interconnected with the input (124) of the feedforward amplifier (123) at a common node (127) and the outputs (130,108) of the feedforward amplifier (123) and the main amplifier (101) are interconnected at a common output node (125). The main amplifier (101) is a replica of the first auxiliary amplifier (102) with an increased gain and the second auxiliary amplifier (122) is a replica of the first auxiliary amplifier (102).

A power amplifier circuit includes an amplifier transistor which amplifies a radio frequency signal applied to its base and outputs the amplified signal; a resistance element having a first end, and a second end electrically connected to the base of the amplifier transistor; a first bias transistor having a collector to which a first voltage is applied, a base to which a first bias voltage is applied, and an emitter electrically connected to the first end of the resistance element and which supplies a bias current to the base of the amplifier transistor through the resistance element; and a second bias transistor having an emitter electrically connected to the emitter of the first bias transistor and the first end of the resistance element, a base to which a second bias voltage is applied, and a collector to which a second voltage lower than the first voltage is applied.