Patent classifications
H03F2200/489
LOW NOISE AMPLIFIER
An amplifier for signal amplification, the amplifier comprising: a signal input arrangement; a signal output arrangement; a first transistor (Q.sub.1); a second transistor (Q.sub.2); and a third transistor (Q.sub.3), wherein: the first (Q.sub.1), second (Q.sub.2) and third (Q.sub.3) transistors are coupled to one another to form a transconductance cell, the transconductance cell is coupled to the signal input arrangement and the signal output arrangement, and the transconductance cell is operable to receive a first signal from the signal input arrangement, amplify the first signal and output an amplified first signal to the signal output arrangement. There is also disclosed a receiver incorporating the amplifier and methods of operating the amplifier.
Optimized Multi Gain LNA Enabling Low Current and High Linearity Including Highly Linear Active Bypass
An LNA having a plurality of paths, each of which can be controlled independently to achieve a gain mode. Each path includes at least an input FET and an output FET coupled in series. A gate of the output FET is controlled to set the gain of the LNA. Signals to be amplified are applied to the gate of the input FET. Additional stacked FETs are provided in series between the input FET and the output FET.
High-frequency semiconductor amplifier
A circuit is formed on an SOI. The bias generator is connected to the gates of first and second transistors. In the bias generator, a first variable current source is connected to the power supply circuit via a power supply node. A third transistor is connected between the first variable current source and a ground-voltage source. A gate thereof is connected to the gate of the first transistor. A first operational amplifier controls a gate voltage of the third transistor so that a voltage at a second node between the first variable current source and the third transistor becomes almost equal to a reference-voltage. A first characteristics changer is connected to the gate of the third transistor or a second node, to change at least one loop gain characteristics and phase characteristics of a loop from the first operational amplifier, through the third transistor, to the first variable current source.
Frequency selective low noise amplifier circuit
Embodiments of the disclosure relate to a frequency selective low noise amplifier (LNA) circuit, which includes a transconductive LNA(s). In one aspect, filter circuitry is provided in a degeneration path of a transconductive LNA(s) to pass in-band frequencies and reject out-of-band frequencies by generating low impedance and high impedance at the in-band frequencies and the out-of-band frequencies, respectively. However, having the filter circuitry in the degeneration path may cause instability in the transconductive LNA. As such, a feedback path is coupled between an input node of the transconductive LNA(s) and the degeneration path to provide a feedback to improve stability of the transconductive LNA(s). In addition, the feedback can help improve impedance match in the frequency selective LNA circuit. As a result, the transconductive LNA(s) is able to achieve improved noise figure (NF) (e.g., below 1.5 dB), return loss, linearity, and stability, without compromising LNA gain.
COMMUNICATIONS DEVICE WITH RECEIVER CHAIN OF REDUCED SIZE
A communications device includes a transmission chain coupled to an antenna a receiver chain coupled to the antenna. The receiver chain includes an amplifier device having an input coupled to the antenna. A controlled switching circuit is included in the amplifier device and is operable to selectively disconnect conduction terminals of an amplifying transistor from power supply terminals when the transmission chain is operating to pass a transmit signal to the antenna.
LNA with variable gain and switched degeneration inductor
A receiver front-end capable of receiving RF inputs having a broad range of levels. The receiver comprises a low-noise amplifier (LNA) operating in a variety of bias modes that cover a large gain range. Branches of the amplifier can be turned on in various combinations to allow selection of different bias modes. A degeneration inductor coupled to the source of the common source FET of each branch has a plurality of taps that are coupled to degeneration switches that can ground the tap to effectively shorten the degeneration inductor and reduce the amount of degeneration inductance. The degeneration inductor and associated switches can be fabricated using one of several physical layouts. Operating the degeneration switches to select the length of the degeneration inductor to match the bias mode reduces changes in the input impedance as different bias modes are selected.
Source Switched Split LNA
A receiver front end capable of receiving and processing intraband non-contiguous carrier aggregate (CA) signals using multiple low noise amplifiers (LNAs) is disclosed herein. A cascode having a common source configured input FET and a common gate configured output FET can be turned on or off using the gate of the output FET. A first switch is provided that allows a connection to be either established or broken between the source terminal of the input FET of each LNA. Further switches used for switching degeneration inductors, gate capacitors and gate to ground caps for each legs can be used to further improve the matching performance of the invention.
Compact architecture for multipath low noise amplifier
Methods and devices used in mobile receiver front end to support multiple paths and multiple frequency bands are described. The presented devices and methods provide benefits of scalability, frequency band agility, as well as size reduction by using one low noise amplifier per simultaneous outputs. Based on the disclosed teachings, variable gain amplification of multiband signals is also presented.
VARIABLE-GAIN AMPLIFIERS WITH CONFIGURABLE IMPEDANCE CIRCUITS
Variable-gain amplifiers can include configurable impedance circuits. For example, a variable-gain amplifier can operate in a plurality of gain modes to amplify a signal with different levels of amplification. The variable-gain amplifier can include a gain circuit configured to amplify a signal and an impedance circuit coupled to the gain circuit. The impedance circuit can include an inductor and a capacitive arm coupled in parallel to the inductor. The impedance circuit can operate based on a current gain mode to change an impedance for the variable-gain amplifier. For example, the capacitive arm can be controlled to change inductance for the different gain modes of the variable-gain amplifier.
HIGH-FREQUENCY SEMICONDUCTOR AMPLIFIER
A circuit is formed on an SOI. The bias generator is connected to the gates of first and second transistors. In the bias generator, a first variable current source is connected to the power supply circuit via a power supply node. A third transistor is connected between the first variable current source and a ground-voltage source. A gate thereof is connected to the gate of the first transistor. A first operational amplifier controls a gate voltage of the third transistor so that a voltage at a second node between the first variable current source and the third transistor becomes almost equal to a reference-voltage. A first characteristics changer is connected to the gate of the third transistor or a second node, to change at least one loop gain characteristics and phase characteristics of a loop from the first operational amplifier, through the third transistor, to the first variable current source.