This disclosure relates to variable-gain amplifiers that include degeneration circuits configured to adapt to a gain mode that is currently being implemented. For example, a variable-gain amplifier can operate in a plurality of gain modes to amplify a signal with different levels of amplification. The variable-gain amplifier can include a gain circuit configured to amplify a signal and a degeneration circuit coupled to the gain circuit. The degeneration circuit can include an inductor and a switching-capacitive arm coupled in parallel to the inductor. The degeneration circuit can operate based on a current gain mode to change an inductance for the variable-gain amplifier.

Techniques for providing low-cost and effective jammer rejection for an amplifier is disclosed. The amplifier includes an input node and an output node, a first transistor and a second transistor, a load circuitry, an inductor, and a capacitor. A first terminal of the first transistor is coupled to a ground. A second terminal of the first transistor is coupled to a first terminal of the second transistor. A second terminal of the second transistor is coupled to the output node. The load circuitry is coupled between a power supply and the second terminal of the second transistor. A first terminal of the inductor is coupled to the ground through a first switch. A first terminal of the capacitor is coupled to the first terminal of the second transistor and a second terminal of the capacitor is coupled to a second terminal of the inductor.

A variable gain low noise amplifier (LNA) and a method for controlling a gain of the variable gain LNA are provided. The variable gain LNA may include a first transistor, a first degeneration inductor, a second transistor and a second degeneration inductor, wherein the first degeneration inductor is coupled to a source terminal of the first transistor, and the second degeneration inductor is coupled to a source terminal of the second transistor. Gate terminals of the first transistor and the second transistor are configured to receive an input signal. The first transistor and the first degeneration inductor belong to a first branch of the variable gain LNA, and the second transistor and the second degeneration inductor belong to a second branch of the variable gain LNA. More particularly, a gain of the variable gain LNA is determined by controlling whether to turn off the second branch.

According to an embodiment of the disclosure, a series or source feedback is provided to a solid-state power amplifier to achieve improved amplifier output power, good impedance match, and low voltage standing wave ratio (VSWR). In an embodiment, an inductive element is coupled to the source of the power amplifier transistor to serve as a series or source feedback for the transistor. In an embodiment, a high-impedance microstrip is provided as an inductive element coupled to the source of the transistor. In an embodiment, a series or source feedback is provided to each amplifier in a multistage amplifier circuit. In an embodiment, a greater series or source feedback is provided at a later stage of a multistage amplifier circuit, whereas a smaller series or source feedback is provided at an earlier stage of the multistage amplifier circuit.

According to an embodiment of the disclosure, a series or source feedback is provided to a solid-state power amplifier to achieve improved amplifier output power, good impedance match, and low voltage standing wave ratio (VSWR). In an embodiment, an inductive element is coupled to the source of the power amplifier transistor to serve as a series or source feedback for the transistor. In an embodiment, a high-impedance microstrip is provided as an inductive element coupled to the source of the transistor. In an embodiment, a series or source feedback is provided to each amplifier in a multistage amplifier circuit. In an embodiment, a greater series or source feedback is provided at a later stage of a multistage amplifier circuit, whereas a smaller series or source feedback is provided at an earlier stage of the multistage amplifier circuit.

Methods and devices to minimize or reduce phase discontinuity between different gain modes (including bypass, active and passive modes) with reduced increase in circuit size (footprint or number of components) and complexity, without impacting other performance parameters, are disclosed. Phase shifter elements that can be disposed in both the active and passive bypass paths are also described. Moreover, devices using the same reconfigurable phase shifter elements in both active and bypass modes are described. Components of the phase shifters can also perform output matching when the phase shifters are implemented as part of an RF receiver front-end.

An amplifier for converting a single-ended input signal to a differential output signal. The amplifier comprises a first transistor, a second transistor, a third transistor and a fourth transistor. The first transistor, configured in common-source or common-emitter mode, receives the single-ended input signal and generates a first part of the differential output signal. The second transistor, also configured in common-source or common-emitter mode, generates a second part of the differential output signal. The third and fourth transistors are capacitively cross-coupled. The amplifier further comprises inductive degeneration such that a source or emitter of the first transistor is connected to a first inductor and a source or emitter of the second transistor is connected to a second inductor.

Bias circuits and methods for silicon-based amplifier architectures that are tolerant of supply and bias voltage variations, bias current variations, and transistor stack height, and compensate for poor output resistance characteristics. Embodiments include power amplifiers and low-noise amplifiers that utilize a cascode reference circuit to bias the final stages of a cascode amplifier under the control of a closed loop bias control circuit. The closed loop bias control circuit ensures that the current in the cascode reference circuit is approximately equal to a selected multiple of a known current value by adjusting the gate bias voltage to the final stage of the cascode amplifier. The final current through the cascode amplifier is a multiple of the current in the cascode reference circuit, based on a device scaling factor representing the relative sizes of the transistor devices in the cascode amplifier and in the cascode reference circuit.

An amplification circuit includes a switch circuit, an amplifier, and a control circuit. The switch circuit has a first terminal coupled to a radio frequency signal input terminal or a system voltage terminal, a second terminal coupled to an input terminal of the amplifier, and a control terminal configured to receive a control signal. The amplifier amplifies a radio frequency signal. The control circuit generates the control signal according to a driving current generated by the amplifier. When the control circuit determines that the amplifier operates in a high power mode, the control circuit controls the control signal to adjust a conducting level between the first terminal and the second terminal of the switch circuit according to the intensity of the driving current.

This disclosure relates to variable-gain amplifiers that include degeneration circuits configured to adapt to a gain mode that is currently being implemented. For example, a variable-gain amplifier can operate in a plurality of gain modes to amplify a signal with different levels of amplification. The variable-gain amplifier can include a gain circuit configured to amplify a signal and a degeneration circuit coupled to the gain circuit. The degeneration circuit can include an inductor and a switching-capacitive arm coupled in parallel to the inductor. The degeneration circuit can operate based on a current gain mode to change an inductance for the variable-gain amplifier.