Voltage regulators and related methods are described. The voltage regulators described in the application may include an operational amplifier, an output transistor, and a signal buffer connected between the operational amplifier and the output transistor. In some embodiments, these voltage regulators are used in connection with memory units. A voltage regulator may be arranged such that the signal amplifier clamps the voltage at the gate of the output transistor to the output voltage when the memory unit is in an idle mode. In this way, when the memory is accessed, the amplitude and duration of output voltage overshoots can be limited, relative to some voltage regulators.

A power amplifier bias circuit with embedded envelope detection includes a bias circuit stage coupled to an envelope detector circuit to increases a bias provided to a power amplifier as a function of an incoming envelope signal. The envelope detector circuit includes a first source/emitter follower transistor, a current source, and a filter to generate a baseband envelope signal. The current source is coupled to an output node of the first source/emitter follower transistor and the filter is also coupled to the output node of the first source/emitter follower transistor. The bias circuit stage includes one or more replica transistors that replicate transistors of the power amplifier or power amplifier core stage, an envelope detector replica transistor and a replica of the current source of the envelope detector circuit.

A bidirectional amplifier includes first and second ports, with a first summing node connected to the first port and a second summing node connected to the second port. First and second gain stages are connected between the first and second summing nodes, respectively, and a first node. First and second feedback stages are also connected between the first and second summing nodes, respectively, and the first node. The amplifier operates in a first mode in which an amplified version of a signal applied to the first port is provided at the second port, or a second mode in which an amplified version of a signal applied to the second port is provided at the first port. The first and second gain stages are preferably first and second common emitter cascode arrangements, and the first and second feedback stages are preferably first and second emitter followers.

A source follower method, system, and apparatus provide rail-to-rail capability to an output voltage terminal of a voltage follower feedback biased CMOS output circuit by providing a control circuit which includes first and second bypass transistors that are connected in parallel between first and second control circuit input/output terminals and controlled, respectively, by first and second control circuit inputs, and which also includes first and second current sources for injecting source and sink currents in the output node as a function, respectively, of a first bypass current through the first bypass transistor which turns ON when the output voltage rises above a top threshold voltage level and of a second bypass current through the second bypass transistor which turns ON when the output voltage falls below a bottom threshold voltage level.

A source follower method, system, and apparatus provide rail-to-rail capability to an output voltage terminal of a voltage follower feedback biased CMOS output circuit by providing a control circuit which includes first and second bypass transistors that are connected in parallel between first and second control circuit input/output terminals and controlled, respectively, by first and second control circuit inputs, and which also includes first and second current sources for injecting source and sink currents in the output node as a function, respectively, of a first bypass current through the first bypass transistor which turns ON when the output voltage rises above a top threshold voltage level and of a second bypass current through the second bypass transistor which turns ON when the output voltage falls below a bottom threshold voltage level.

An electronic circuit includes image acquisition cells, wherein each cell has a photodetector coupled to a first node of the cell, and an amplifying transistor having a gate connected to the first node, a conduction node coupled to an output of the cell, and a node for controlling a back gate voltage. The amplifying transistor is configured so that its threshold voltage varies according to the back gate voltage. A control circuit adjusts a voltage applied to the control node of the back gate voltage of the amplifying transistor of one of the cells according to a comparison of the voltage present at the cell output and a reference voltage.

Provided herein are amplifiers, such as buffers, with increased headroom. An amplifier stage includes a follower transistor and current source configured to receive a power supply voltage comprising an alternating current component and a direct current component. The alternating current component of the power supply voltage has substantially the same frequency and magnitude as the input signal received by the follower transistor. In radio frequency (RF) and intermediate frequency (IF) buffer applications, for example, the increased headroom can allow for linear buffering of an input signals with increased amplitude so that the output power one decibel (OP1dB) compression point can be increased.

An input stage of a chip includes a source driver and a sensing and clamping circuit. The source follower is arranged for receiving an AC-coupled signal to generate an output signal at an output terminal. The sensing and clamping circuit is coupled to the source follower, and is arranged for clamping the output terminal of the source follower at a fixed DC voltage.

A source follower with an input node and an output node includes a first transistor, a second transistor, and a DC (Direct Current) tracking circuit. The first transistor has a control terminal, a first terminal coupled to a first node, and a second terminal coupled to a second node. The second transistor has a control terminal, a first terminal coupled to a ground voltage, and a second terminal coupled to the first node. The DC tracking circuit sets the second DC voltage at the second node to a specific level. The specific level is determined according to the first DC voltage at the first node. The output node of the source follower is coupled to the first node.

A voltage regulator is disclosed. The voltage regulator is cascaded, including first and second stages. The first stage may be a capacitor-less first stage that includes a source follower implemented with a first PMOS transistor, with the first PMOS transistor receiving a first reference voltage on its respective gate terminal. The first stage is coupled to receive a first voltage from an external voltage supply, and to provide a second voltage to the second stage. The second stage may be directly and exclusively coupled to the first stage, with no capacitor or connection for one coupled to the first stage output. The second stage may provide an output voltage, on an output node, with the output voltage being less than the second voltage.