Methods and devices for reducing gate node instability of a differential cascode amplifier are presented. Ground return loops, and therefore corresponding parasitic inductances, are eliminated by using voltage symmetry at nodes of two cascode amplification legs of the differential cascode amplifier. Series connected capacitors are coupled between gate nodes of pairs of cascode amplifiers of the two cascode amplification legs so to create a common node connecting the two capacitors. In order to reduce peak to peak voltage variation at the common node under large signal conditions, a shunting capacitor is connected to the common node.

An ultrasound probe buffer is provided. The ultrasound probe buffer may include a high impedance amplifier having a common-source core stage with series-series local feedback. The high impedance amplifier may include a first MOSFET and a second MOSFET, wherein a source terminal of the first MOSFET is coupled to a source terminal of the second MOSFET.

Apparatus (1) comprises envelope signal amplification circuitry (11) configured to receive an input envelope signal (ENV_in) indicative of an envelope of an input radio frequency signal (RF_in) and to output an amplified envelope signal (ENV_amp); and a radio frequency power amplifier (12) configured to receive a radio frequency control signal which is dependent on the input radio frequency signal(RF_in) and the input envelope signal (ENV_in), using the amplified envelope signal (ENV_amp) as its supply voltage, to output an amplified radio frequency signal (RF_amp). A method for amplification the radio frequency signal is also provided.

A multi-gain LNA with inductive source degeneration is presented. The inductive source degeneration is provided via a tunable degeneration network that includes an inductor in parallel with one or more switchable shunting networks. Each shunting network includes a shunting capacitor that can selectively be coupled in parallel to the inductor. A capacitance of the shunting capacitor is calculated so that a combined impedance of the inductor and the shunting capacitor at a narrowband frequency of operation is effectively an inductance. The inductance is calculated according to a desired gain of the LNA. According to one aspect, the switchable shunting network includes a resistor in series connection with the shunting capacitor to provide broadband frequency response stability of the tunable degeneration network. According to another aspect, the LNA includes a plurality of selectable branches to further control gain of the LNA.

A power amplifier circuit includes an amplifier transistor which amplifies a radio frequency signal applied to its base and outputs the amplified signal; a resistance element having a first end, and a second end electrically connected to the base of the amplifier transistor; a first bias transistor having a collector to which a first voltage is applied, a base to which a first bias voltage is applied, and an emitter electrically connected to the first end of the resistance element and which supplies a bias current to the base of the amplifier transistor through the resistance element; and a second bias transistor having an emitter electrically connected to the emitter of the first bias transistor and the first end of the resistance element, a base to which a second bias voltage is applied, and a collector to which a second voltage lower than the first voltage is applied.

An amplifier includes a semiconductor die and a substrate that is distinct from the semiconductor die. The semiconductor die includes a III-V semiconductor substrate, a first RF signal input terminal, a first RF signal output terminal, and a transistor (e.g., a GaN FET). The transistor has a control terminal electrically coupled to the first RF signal input terminal, and a current-carrying terminal electrically coupled to the first RF signal output terminal. The substrate includes a second RF signal input terminal, a second RF signal output terminal, circuitry coupled between the second RF signal input terminal and the second RF signal output terminal, and an electrostatic discharge (ESD) protection circuit. The amplifier also includes a connection electrically coupled between the ESD protection circuit and the control terminal of the transistor. The substrate may be another semiconductor die (e.g., with a driver transistor and/or impedance matching circuitry) or an integrated passive device.

An amplifier includes a semiconductor die and a substrate that is distinct from the semiconductor die. The semiconductor die includes a first RF signal input terminal, a first RF signal output terminal, and a transistor. The transistor has a control terminal electrically coupled to the first RF signal input terminal, and a current-carrying terminal electrically coupled to the first RF signal output terminal. The substrate includes a second RF signal input terminal, a second RF signal output terminal, circuitry coupled between the second RF signal input terminal and the second RF signal output terminal, and an electrostatic discharge (ESD) protection circuit. The amplifier also includes a connection electrically coupled between the ESD protection circuit and the control terminal of the transistor. The substrate may be another semiconductor die (e.g., with a driver transistor and/or impedance matching circuitry) or an integrated passive device.

Certain aspects of the present disclosure provide an amplifier. The amplifier generally includes an amplifier core circuit configured to amplify a radio frequency signal and having a first output and a second output; a transformer coupled to the amplifier core circuit, the transformer having a primary winding and a secondary winding, the primary winding being coupled to the first output and the second output of the amplifier core circuit, the secondary winding being coupled to an output node of the amplifier; and a variable resistance circuit coupled in parallel with the primary winding.

A power amplifier with feedback ballast resistance is disclosed. In one aspect, a power amplifier cell may receive a bias signal from a bias circuit where the bias circuit includes a feedback loop having an impedance that, from the perspective of the bias signal is relatively low impedance, but from a ballast thermal control perspective provides sufficient resistance to avoid thermal runaway. In exemplary aspects, this feedback loop may be extended to operate with multiple power amplifier cells and provide differential mode thermal control optimized for individual cell bias signal control and common mode thermal control optimized for thermal control of the collective power amplifier cells of the power amplifier.

Apparatus and methods for compensating supply sensitive circuits for supply voltage variation are provided. In certain embodiments, an electronic system includes a power supply that outputs a supply voltage having a nominal voltage level, a supply conductor for routing the supply voltage, and a group of integrated circuits (ICs) that each receive the supply voltage from the supply conductor. Each IC includes a supply sensing circuit that generates a sense signal based on a local voltage level of the supply voltage at the IC, a bias control circuit that adjusts a bias signal based on the sense signal to account for a difference between the nominal voltage level and the local voltage level of the supply voltage, and a signal processing circuit biased by the bias signal.