Patent classifications
H03G1/0005
Systems and methods for digital predistortion to mitigate power amplifier bias circuit effects
A digital predistortion (DPD) system includes an input configured to receive an input signal. In some examples, a first signal path configured to generate a first signal based on the input signal. In some examples, an error model provider configured to generate an error model signal modeled after a gate bias error voltage associated with the DPD system. In some examples, a first combiner configured to combine the first signal and the error model signal to generate a first intermediate signal, and the DPD system generates an output signal based at least on the first intermediate signal.
Asymmetric multi-channel audio dynamic range processing
A method for audio processing includes receiving multiple electrical signals to be transmitted in parallel via multiple respective audio channels. Multiple respective weights are assigned to the multiple electrical signals, wherein at least two of the weights differ from one another. An instantaneous gain is calculated, to be applied to the multiple electrical signals. The instantaneous gain depends on (i) instantaneous amplitudes of the multiple electrical signals, and (ii) the weights assigned to the multiple electrical signals. The instantaneous gain is applied to the multiple electrical signals, and the multiple electrical signals are transmitted via the multiple respective audio channels.
Active Device Which has a High Breakdown Voltage, is Memory-Less, Traps Even Harmonic Signals and Circuits Used Therewith
An active device and circuits utilized therewith are disclosed. In an aspect, the active device comprises an n-type transistor having a drain, gate and bulk and a p-type transistor having a drain, gate and bulk. The n-type transistor and the p-type transistor include a common source. The device includes a first capacitor coupled between the gate of the n-type transistor and the gate of the p-type transistor, a second capacitor coupled between the drain of the n-type transistor and the drain of p-type transistor and a third capacitor coupled between the bulk of the n-type transistor and the bulk of p-type transistor. The active device has a high breakdown voltage, is memory less and traps even harmonic signals.
Stereo audio system and method
A circuit receives a first input signal and a second input signal, and provides three driving signals to three output wires, respectively. A first driving signal is provided to a first output wire, and is based on a difference between the first input signal and the second input signal. A second driving signal is provided to a second output wire, and is based on a sum of the first input signal and the second input signal. A third driving signal is provided to a third output wire, and is based on an inverse of the first driving signal. A first output signal between the first output wire and the second output wire is based on the second input signal. A second output signal between the third output wire and the second output wire is based on the first input signal.
STEREO AUDIO SYSTEM AND METHOD
A circuit receives a first input signal and a second input signal, and provides three driving signals to three output wires, respectively. A first driving signal is provided to a first output wire, and is based on a difference between the first input signal and the second input signal. A second driving signal is provided to a second output wire, and is based on a sum of the first input signal and the second input signal. A third driving signal is provided to a third output wire, and is based on an inverse of the first driving signal. A first output signal between the first output wire and the second output wire is based on the second input signal. A second output signal between the third output wire and the second output wire is based on the first input signal.
Active device which has a high breakdown voltage, is memory-less, traps even harmonic signals and circuits used therewith
An active device and circuits utilized therewith are disclosed. In an aspect, the active device comprises an n-type transistor having a drain, gate and bulk and a p-type transistor having a drain, gate and bulk. The n-type transistor and the p-type transistor include a common source. The device includes a first capacitor coupled between the gate of the n-type transistor and the gale of the p-type transistor, a second capacitor coupled between the drain of the n-type transistor and the drain of p-type transistor and a third capacitor coupled between the bulk of the n-type transistor and the bulk of p-type transistor. The active device has a high breakdown voltage, is memory less and traps even harmonic signals.
VARIABLE GAIN AMPLIFIERS FOR COMMUNICATION SYSTEMS
The present invention is directed to electrical circuits and techniques thereof. In various embodiments, the present invention provides a variable gain amplifier architecture that includes a continuous-time linear equalizer (CTLE) section and a variable gain amplifier (VGA) section. The CTLE section provides both a pair of equalized data signals and a common mode voltage. A DAC generates a control signal based on a control code. The VGA section amplifies the pair of equalized data signals by an amplification factor using a transistor whose resistance value is based on both the common mode voltage and the control signal. There are other embodiments as well.
SYSTEM FOR LOUDSPEAKER REAL TIME STATE VARIABLE PREDICTION WITH LIMITING AND LINEAR COMPENSATION
A loudspeaker real-time state variable prediction system may include a loudspeaker having a voice coil and a magnet, and a non-linear excursion model configured to estimate non-linear excursion of the loudspeaker. The system may further include a thermal model configured to utilize thermal parameters and frequency based on at least one thermal property of the loudspeaker, and a gain adjustment thermal limiter configured to apply a gain reduction an incoming audio signal to protect the loudspeaker from thermal overload.
Variable gain amplifiers for communication systems
The present invention is directed to electrical circuits and techniques thereof. In various embodiments, the present invention provides a variable gain amplifier architecture that includes a continuous-time linear equalizer (CTLE) section and a variable gain amplifier (VGA) section. The CTLE section provides both a pair of equalized data signals and a common mode voltage. A DAC generates a control signal based on a control code. The VGA section amplifies the pair of equalized data signals by an amplification factor using a transistor whose resistance value is based on both the common mode voltage and the control signal. There are other embodiments as well.
Asymmetric multi-channel audio dynamic range processing
A method for audio processing includes receiving multiple electrical signals to be transmitted in parallel via multiple respective audio channels. Multiple respective weights are assigned to the multiple electrical signals, wherein at least two of the weights differ from one another. An instantaneous gain is calculated, to be applied to the multiple electrical signals. The instantaneous gain depends on (i) instantaneous amplitudes of the multiple electrical signals, and (ii) the weights assigned to the multiple electrical signals. The instantaneous gain is applied to the multiple electrical signals, and the multiple electrical signals are transmitted via the multiple respective audio channels.