An apparatus and method for processing signals in the analog domain. A signal is derived from analog circuit properties that is shift and scale invariant. Although the circuit properties are not quantized as in traditional digital signal processing, the signal is immune from effects of the properties, such as common mode noise, absolute voltage or current level, finite settling time, etc., as a digital signal would be. The shift and scale invariance allows for mathematical operations of addition, subtraction, multiplication and division of signals. By combining these operations, various circuits may be constructed, including a voltage controlled amplifier, a time gain amplifier, and an analog-to-digital converter. The circuits are constructed using almost no non-linear, active devices, and will thus use less power for a given speed than comparable digital devices, and will often be faster as there are no delay elements and no need to wait for the circuit properties to settle.

A speech intelligibility enhancing system for difficult acoustical conditions is disclosed, the speech intelligibility enhancing system comprising at least one ear plug (201) for insertion in an ear canal (218) of a person, the at least one ear plug being arranged with an ear canal facing portion (401) and an environment facing portion (402), and the at least one ear plug comprising an acoustically attenuating path (214; 214, 213) comprising a vent (214) coupling said environment facing portion (402) with said ear canal facing portion (401); and an electroacoustic path (202, 204, 209; 202, 203, 204, 208, 209, 210, 211, 212) comprising a microphone (202) at said environment facing portion (402), a variable gain (204) and a loudspeaker (209) at said ear canal facing portion (401); wherein said acoustically attenuating path (214; 214, 213) is arranged with a transfer function from said environment facing portion (402) to said ear canal facing portion (401) having a low pass characteristic having a low pass cut¬off frequency and said low pass characteristic attenuating sound by a nominal attenuation (Go) for frequencies below said cut-off frequency.

Disclosed herein is a DC offset cancellation circuit. The DC offset cancellation circuit includes a DC feedback unit configured to vary a DC feedback (DCFB) bandwidth to add at least one mid-bandwidth to the DCFB bandwidth and to provide a delay time in each case in order to reduce the DC droop error that occurs in switching from the high bandwidth (BW) to the mid-BW or from the mid-BW mode to the low BW mode, such that stable settling is ensured.

A programmable amplifier circuit includes an amplifier, an input capacitor coupled to an input of the amplifier, a feedback capacitor coupled to the input of the amplifier and an output of the amplifier, and a switched-capacitor resistor circuit. The switched-capacitor resistor circuit is coupled between the input of the amplifier and the output of the amplifier, and configured for simulating a feedback resistor element to provide a resistance for a feedback path of the amplifier by using at least one capacitor placed between the input of the amplifier and the output of the amplifier to avoid leakage current(s) flowing back to an input of the amplifier.

An integrated circuit amplifier configurable to be either a programmable gain amplifier or an operational amplifier comprises two output blocks, one output block is optimized for programmable gain amplifier operation, and the other output block is optimized for operational amplifier applications. A common single input stage, input offset calibration and bias generation circuits are used with either amplifier configuration. Thus duplication of the input stage, offset calibration and bias generation circuits are eliminated while still selectably providing for either a programmable gain amplifier or operational amplifier configuration.

A digitally-controlled transimpedance amplifier (TIA) circuit is provided in which a plurality of feedback loops are digitally controlled, including, but not limited to, the DC offset cancellation loop, the variable gain control loop, and the TIA feedback impedance adjustment loop. The digitally-controlled TIA circuit includes digital loop-control circuitry that consumes less area on the TIA IC chip than the analog circuitry traditionally used to perform the feedback loop control in the analog domain. In addition, because digital logic continues to shrink as IC processes continue to evolve, the size of the IC chip packages will further decrease over time, leading to a smaller footprint in systems in which they are employed. The digital loop control circuitry is also capable of independently varying the gains of multiple gain stages of the variable gain control circuit to provide better control over the gain stages and better overall performance of the TIA circuit.

A device includes: a transistor having an input terminal configured to receive an input signal and to amplify the input signal; a bias current source configured to set a bias current of the input terminal of the transistor, the bias current source having a control input for receiving a control signal for selecting the bias current to have one of a plurality of selectable bias current levels; a bias resistance connected between the bias current source and the input terminal of the transistor; a bypass switch for selectively bypassing a first part of the bias resistance; and a control circuit for controlling the bypass switch to bypass the part of the bias resistance for a predefined time period in response to a change in the bias current level, and for controlling the bypass switch to stop bypassing the first part of the bias resistance after the predefined time period expires.

An example automatic gain control (AGC) circuit includes a base current-gain circuit having a programmable source degeneration resistance responsive to first bits of an AGC code word. The AGC circuit further includes a programmable current-gain circuit, coupled between an input and an output of the base current-gain circuit, having a programmable current source responsive to second bits of the AGC code word. The AGC circuit further includes a bleeder circuit, coupled to the output of the base current-gain circuit, having a programmable current source responsive to logical complements of the second bits of the AGC code word. The AGC circuit further includes a load circuit coupled to the output of the base current-gain circuit.

A method and system is presented for coordinating the transmission of supplemental digital data to accompany broadcast data, and in particular, analog radio broadcasts, among a plurality of broadcasters. The supplemental digital data may provide information about the particular broadcast data being transmitted (i.e. cut data) or may be supplemental to such data (i.e. news, weather and traffic data). The supplemental digital data to be presented is sorted based on particular algorithms which may take into account broadcaster-specified criteria such as target audience, time of day, type of broadcast data presented, and the like. The supplemental digital data may be audio data, visual data, or audio-visual data for presentation with the broadcast data. The supplemental digital data may further be advertisement data. The advertisement data may be sold by the broadcasters or the party coordinating the IBOC transmission of the supplemental digital data. The supplemental digital data may play simultaneously with muted broadcast data or at a user-specified time.

A variable gain amplifier and an electronic apparatus. The variable gain amplifier includes a first transconductance stage circuit and a second transconductance stage circuit, where the first transconductance stage circuit includes a first amplifying circuit and a second amplifying circuit, the second transconductance stage circuit includes a third amplifying circuit and a fourth amplifying circuit, the first amplifying circuit and the fourth amplifying circuit form a differential input pair, and the second amplifying circuit and the third amplifying circuit form a differential input pair, and where each amplifying circuit of the first amplifying circuit, the second amplifying circuit, the third amplifying circuit, and the fourth amplifying circuit includes a plurality of parallel transistors, and bias control of the plurality of transistors is independent of each other.