The present invention is directed to electrical circuits and techniques thereof. In various embodiments, the present invention provides a variable gain amplifier architecture that includes a continuous-time linear equalizer (CTLE) section and a variable gain amplifier (VGA) section. The CTLE section provides both a pair of equalized data signals and a common mode voltage. A DAC generates a control signal based on a control code. The VGA section amplifies the pair of equalized data signals by an amplification factor using a transistor whose resistance value is based on both the common mode voltage and the control signal. There are other embodiments as well.

The present invention is directed to electrical circuits and techniques thereof. In various embodiments, the present invention provides a variable gain amplifier architecture that includes a continuous-time linear equalizer (CTLE) section and a variable gain amplifier (VGA) section. The CTLE section provides both a pair of equalized data signals and a common mode voltage. A DAC generates a control signal based on a control code. The VGA section amplifies the pair of equalized data signals by an amplification factor using a transistor whose resistance value is based on both the common mode voltage and the control signal. There are other embodiments as well.

A power detector has a signal input terminal, N limiting amplifiers, N rectifiers and a signal output terminal. N is an integer greater than 1. The signal input terminal receives an input signal, and the signal output terminal outputs a detection signal. The N limiting amplifiers generate N amplified signals according to N attenuated signals having different attenuation. Each limiting amplifier receives one of the N attenuated signals and outputs one of the N amplified signals. Each rectifier receives a corresponding amplified signal and outputs a rectified signal. The detection signal is associated with the sum of N rectified signals outputted from the N rectifiers, and all transistors of the power detector are bipolar junction transistors.

Disclosed herein is a device and method for intelligently reducing power consumption in an audio amplifier in the device, and in particular Class-D amplifiers, through the use of metadata associated with settings of the playback device and/or content to be played on the playback device. The device includes components for analyzing the settings and content metadata and regulates the voltage provided to the audio amplifier based on this analysis.

Disclosed herein is a device and method for intelligently reducing power consumption in an audio amplifier in the device, and in particular Class-D amplifiers, through the use of metadata associated with settings of the playback device and/or content to be played on the playback device. The device includes components for analyzing the settings and content metadata and regulates the voltage provided to the audio amplifier based on this analysis.

The present invention is directed to electrical circuits and techniques thereof. In various embodiments, the present invention provides a variable gain amplifier architecture that includes a continuous-time linear equalizer (CTLE) section and a variable gain amplifier (VGA) section. The CTLE section provides both a pair of equalized data signals and a common mode Voltage. A DAC generates a control signal based on a control code. The VGA section amplifies the pair of equalized data signals by an amplification factor using a transistor whose resistance value is based on both the common mode voltage and the control signal. There are other embodiments as well.

The present invention is directed to electrical circuits and techniques thereof. In various embodiments, the present invention provides a variable gain amplifier architecture that includes a continuous-time linear equalizer (CTLE) section and a variable gain amplifier (VGA) section. The CTLE section provides both a pair of equalized data signals and a common mode Voltage. A DAC generates a control signal based on a control code. The VGA section amplifies the pair of equalized data signals by an amplification factor using a transistor whose resistance value is based on both the common mode voltage and the control signal. There are other embodiments as well.

An improved dynamics processing control system incorporates an integration release window to virtually eliminate ripple in the final control signal used to control a Voltage Controlled Amplifier in a signal processor. The input audio signal is level detected using a logarithmic level detector and filtered to provide a very fast time constant. The fast release time constant signal is clamped at a maximum level equal to the user defined threshold and filtered by a second filter providing a very long release time constant. The long release time constant is dynamically varied by the fast time constant to provide an adaptive slow time constant. The fast time constant signal modifies the adaptive slow time constant when the difference between the fast time constant and the slow time constant exceeds a predefined integration release window. The integration release window is based on a minimum number of decibels which is larger than the maximum possible ripple in the fast time constant signal. The integration release window tracks the adaptive slow time constant signal to maintain the integration release window over the entire release range of the adaptive slow time constant decay. Once the difference between the fast time constant signal and adaptive slow time constant signal is less than the integration release window, the slow release signal reverts to the un-altered slow time constant release response.

An improved dynamics processing control system incorporates an integration release window to virtually eliminate ripple in the final control signal used to control a Voltage Controlled Amplifier in a signal processor. The input audio signal is level detected using a logarithmic level detector and filtered to provide a very fast time constant. The fast release time constant signal is clamped at a maximum level equal to the user defined threshold and filtered by a second filter providing a very long release time constant. The long release time constant is dynamically varied by the fast time constant to provide an adaptive slow time constant. The fast time constant signal modifies the adaptive slow time constant when the difference between the fast time constant and the slow time constant exceeds a predefined integration release window. The integration release window is based on a minimum number of decibels which is larger than the maximum possible ripple in the fast time constant signal. The integration release window tracks the adaptive slow time constant signal to maintain the integration release window over the entire release range of the adaptive slow time constant decay. Once the difference between the fast time constant signal and adaptive slow time constant signal is less than the integration release window, the slow release signal reverts to the un-altered slow time constant release response.

An electronic device is provided. The electronic device includes an integrated circuit (IC); a sonic vibrator arranged on one side of the IC; a speaker; and a processor configured to: control the speaker based on a sound signal, and filter a low-frequency band signal that is less than or equal to a threshold frequency from the sound signal and provide the low-frequency band signal to the sonic vibrator.