A capacitor has a variable capacitance settable by a bias voltage. A method for setting the bias voltage including the steps of: (a) injecting a constant current to bias the capacitor; (b) measuring the capacitor voltage at the end of a time interval; (c) calculating the capacitance value obtained at the end of the time interval; (d) comparing this value with a desired value; and (e) repeating steps (a) to (d) so as long as the calculated value is different from the set point value. When calculated value matches the set point value; the measured capacitor voltage is stored as a bias voltage to be applied to the capacitor for setting the variable capacitance.

A capacitor has a variable capacitance settable by a bias voltage. A method for setting the bias voltage including the steps of: (a) injecting a constant current to bias the capacitor; (b) measuring the capacitor voltage at the end of a time interval; (c) calculating the capacitance value obtained at the end of the time interval; (d) comparing this value with a desired value; and (e) repeating steps (a) to (d) so as long as the calculated value is different from the set point value. When calculated value matches the set point value; the measured capacitor voltage is stored as a bias voltage to be applied to the capacitor for setting the variable capacitance.

A capacitor has a variable capacitance settable by a bias voltage. A method for setting the bias voltage including the steps of: (a) injecting a constant current to bias the capacitor; (b) measuring the capacitor voltage at the end of a time interval; (c) calculating the capacitance value obtained at the end of the time interval; (d) comparing this value with a desired value; and (e) repeating steps (a) to (d) so as long as the calculated value is different from the set point value. When calculated value matches the set point value; the measured capacitor voltage is stored as a bias voltage to be applied to the capacitor for setting the variable capacitance.

A capacitor has a variable capacitance settable by a bias voltage. A method for setting the bias voltage including the steps of: (a) injecting a constant current to bias the capacitor; (b) measuring the capacitor voltage at the end of a time interval; (c) calculating the capacitance value obtained at the end of the time interval; (d) comparing this value with a desired value; and (e) repeating steps (a) to (d) so as long as the calculated value is different from the set point value. When calculated value matches the set point value; the measured capacitor voltage is stored as a bias voltage to be applied to the capacitor for setting the variable capacitance.

A discrete capacitance switching circuit includes a DC decoupling capacitor connected between a power node that receives an AC signal and a first node, a diode connected between the first node and a second node, a unit capacitor connected between the second node and a reference node that receives a ground voltage, and a bias circuit. The bias circuit is configured to apply a first DC voltage to the first node and apply a second DC voltage to the second node. The applied first and second DC voltages control a switching operation of the diode.

An electronic control device includes: a first input-output terminal and a second input-output terminal through which differential signals are input and output; a transceiver integrated circuit (IC) that transmits and receives the differential signals; a first line that connects the first input-output terminal and the transceiver IC; and a second line that connects the second input-output terminal and the transceiver IC. A first capacitance that is a capacitance between the first line and a ground is at least 80 pF and at most 220 pF, and a second capacitance that is a capacitance between the second line and the ground is at least 80 pF and at most 220 pF.

A variable capacitor bank includes a conductive housing and a port extending through the housing. An electrical bus is disposed within the conductive housing and coupled to the port. The variable capacitor bank further includes capacitor modules disposed within the housing. Each capacitor module includes a module input electrically coupled to the electrical bus and a switched capacitor branch electrically coupled to the module input, the switched capacitor branch including a capacitor and a switch element in series with the capacitor. In certain implementations, one or more of the capacitor modules may include at least one second switched capacitor branch. The capacitor modules may further include an unswitched, or floor, capacitor that provides a minimum or otherwise known capacitance of the capacitor module. Each capacitor module may further be grounded by being electrically coupled to the conductive housing.

The present disclosure may include, for example, a tunable capacitor having a decoder for generating a plurality of control signals, and an array of tunable switched capacitors comprising a plurality of fixed capacitors coupled to a plurality of switches. The plurality of switches can be controlled by the plurality of control signals to manage a tunable range of reactance of the array of tunable switched capacitors. Additionally, the array of tunable switched capacitors is adapted to have non-uniform quality (Q) factors. Additional embodiments are disclosed.

The present disclosure may include, for example, a tunable capacitor having a decoder for generating a plurality of control signals, and an array of tunable switched capacitors comprising a plurality of fixed capacitors coupled to a plurality of switches. The plurality of switches can be controlled by the plurality of control signals to manage a tunable range of reactance of the array of tunable switched capacitors. Additionally, the array of tunable switched capacitors is adapted to have non-uniform quality (Q) factors. Additional embodiments are disclosed.

A programmable resistor can provide discrete logarithmic (linear-in-dB) gain control. It can include multiple like programmable resistor subnetworks or cells, such as can be connected in parallel, such as according to a decoding scheme. The subnetworks can be configured to cover a subrange such as [0 dB, 6 dB) relative to the maximum resistance value. Coarse increments of 6 dB can be further added to this range by successively doubling the number of subnetworks that are connected in parallel. An additional decoder help ensure a linear control curve, free of dead zones or other nonlinearities. The programmable resistor can be suitable for use in such circuits as programmable-gain amplifiers, filters, or more complex networks, such as where the resistance can be programmed as a function of a digital code. An example including a tuning circuit for a variable gain active filter is described.