H03H7/30

Efficient multi-mode DFE
11005567 · 2021-05-11 · ·

An illustrative SerDes receiver includes: a front-end filter, a precomputation unit, a selection element, and a controller. The front end filter converts a receive signal into a linearly-equalized signal. The precomputation unit accepts the linearly-equalized signal with or without a subtracted feedback signal, and employs a set of comparators with threshold values that depend on a first post-cursor ISI value F.sub.1, the set of comparators operating to generate a set of tentative symbol decisions. The selection element derives a selected symbol decision from each set of tentative symbol decisions, thereby deriving a sequence of symbol decisions from the receive signal. The controller constrains F.sub.1 if the receive signal uses a PAM4 signal constellation, setting F.sub.1 to equal zero if the receive signal is conveyed via a low-loss channel and to equal one if the receive signal is conveyed via a high-loss channel.

Efficient multi-mode DFE
11005567 · 2021-05-11 · ·

An illustrative SerDes receiver includes: a front-end filter, a precomputation unit, a selection element, and a controller. The front end filter converts a receive signal into a linearly-equalized signal. The precomputation unit accepts the linearly-equalized signal with or without a subtracted feedback signal, and employs a set of comparators with threshold values that depend on a first post-cursor ISI value F.sub.1, the set of comparators operating to generate a set of tentative symbol decisions. The selection element derives a selected symbol decision from each set of tentative symbol decisions, thereby deriving a sequence of symbol decisions from the receive signal. The controller constrains F.sub.1 if the receive signal uses a PAM4 signal constellation, setting F.sub.1 to equal zero if the receive signal is conveyed via a low-loss channel and to equal one if the receive signal is conveyed via a high-loss channel.

Integrating Volterra series model and deep neural networks to equalize nonlinear power amplifiers

The nonlinearity of power amplifiers (PAs) has been a severe constraint in performance of modern wireless transceivers. This problem is even more challenging for the fifth generation (5G) cellular system since 5G signals have extremely high peak to average power ratio. Nonlinear equalizers that exploit both deep neural networks (DNNs) and Volterra series models are provided to mitigate PA nonlinear distortions. The DNN equalizer architecture consists of multiple convolutional layers. The input features are designed according to the Volterra series model of nonlinear PAs. This enables the DNN equalizer to effectively mitigate nonlinear PA distortions while avoiding over-fitting under limited training data. The non-linear equalizers demonstrate superior performance over conventional nonlinear equalization approaches.

Iterative channel estimation and equalization with superimposed reference signals

In a transmitter apparatus, a known reference signal is superimposed on top of a data signal that is typically not known a priori to a receiver and the combined signal is transmitted. At a receiver, an iterative channel estimation and equalization technique is used to recover the reference signal and the unknown data signal. In the initial iteration, the known reference signal is recovered by treating the data signal as noise. Subsequent iterations are used to improve estimation of received reference signal and the unknown data signal.

Signal transmission method and system and retimer

A retimer is provided. The retimer includes: a data channel circuit, configured to implement, under a function of a current phase locked loop, equalization processing-based transparent transmission of a signal between a first communications device and a second communications device; and the link adjustment circuit, configured to: when determining, based on link status information of the data channel circuit, that a rate of a link needs to be changed, configure an operating parameter of a target phase locked loop as an operating parameter corresponding to a changed rate; and switch the currently used phase locked loop to the target phase locked loop when detecting that the link enters a rate-changing state, where the data channel circuit is further configured to implement, under a function of the target phase locked loop, the transparent transmission of a signal between the first communications device and the second communications device.

Signal transmission method and system
10958488 · 2021-03-23 · ·

This application provides a signal transmission method and system, and relates to the field of communications technologies. The system includes an equalization module, a first decoder, and a feedback module. The equalization module includes at least two multi-symbol detectors. The feedback module is connected to the first decoder and the at least two multi-symbol detectors. The equalization module performs equalization processing on convolutional data flows to obtain an equalized data flow. In this process, each multi-symbol detector performs multi-symbol detection processing on a convolutional data flow input into the multi-symbol detector. The first decoder decodes the equalized data flow to obtain a decoded data flow. The feedback module feeds back a feedback data flow to the at least two multi-symbol detectors. The equalization module performs equalization processing on the convolutional data flows based on the feedback data flow.

Data transmission circuit

A data transmission circuit includes: a main driver circuit suitable for driving data to an output line; an amplitude equalization window generator circuit suitable for detecting the data transitioning from a first level to a second level; an auxiliary driver circuit suitable for driving the output line with the second level in response to a detection result of the amplitude equalization window generator circuit; and a phase equalization window generator circuit suitable for detecting whether the data consecutively has the first level, wherein the main driver circuit changes a time point of driving the data in response to a detection result of the phase equalization window generator circuit.

Method and apparatus for adaptive signal processing

A method for adaptive signal processing is provided. In the method, a second vector is obtained by initializing a first vector without regularization of a cost function. The cost function is regularized with the first vector and the second vector as variables. The first vector is updated based on an input signal, according to the regularized cost function. Then, an output signal is provided based on the updated first vector. The second vector is updated based on the update of the first vector. An apparatus for adaptive signal processing is provided accordingly. The method and the apparatus are well compatible with existing adaptive signal processing. The convergence coefficients of the adaptive filter system become more stable. Moreover, impact of an extra penalty added to the cost function on a bias can be minimized, and the increased complexity of the system is very limited.

Reception circuit, receiver, and reception control method
10944601 · 2021-03-09 · ·

A reception circuit includes: a first equalizer configured to equalize a reception waveform; a second equalizer configured to equalize an input waveform from the first equalizer; a monitor configured to monitor magnitude of the input waveform; and a controller configured to generate a gain control code used for setting a gain of the first equalizer and a threshold voltage control code used for setting a threshold voltage to be compared with the input waveform in the second equalizer, in accordance with a monitoring result of the magnitude obtained by the monitor.

Integrating volterra series model and deep neural networks to equalize nonlinear power amplifiers

The nonlinearity of power amplifiers (PAs) has been a severe constraint in performance of modern wireless transceivers. This problem is even more challenging for the fifth generation (5G) cellular system since 5G signals have extremely high peak to average power ratio. Nonlinear equalizers that exploit both deep neural networks (DNNs) and Volterra series models are provided to mitigate PA nonlinear distortions. The DNN equalizer architecture consists of multiple convolutional layers. The input features are designed according to the Volterra series model of nonlinear PAs. This enables the DNN equalizer to effectively mitigate nonlinear PA distortions while avoiding over-fitting under limited training data. The non-linear equalizers demonstrate superior performance over conventional nonlinear equalization approaches.