A joining device includes: a first circuit in which a primary-side winding of a first transformer and a first capacitor are connected; a second circuit in which a primary-side winding of a second transformer and a second capacitor are connected; an electrode connected to secondary-side winding of the first transformer and secondary-side winding of the second transformer; and a charge switch configured to switch between energization/de-energization of the first and second capacitors from a power supply without the transformers being interposed. The first circuit has a first discharge switch and the second circuit has a second discharge switch. A method for manufacturing a joined object includes, by using the joining device, supplying an object to be joined to be sandwiched by the electrode; causing a current to flow through the electrode that sandwiches the object to be joined to join the object to be joined.

Examples of amplifiers and n.sup.th-order loop filters thereof are configured to enable fast and robust recovery from saturation, while limiting signal distortion at or near full power delivery across multiple process and temperature corners. An example n.sup.th-order loop filter comprises n series-coupled resistor-capacitor (RC) integrators. In an example, each of the second RC integrator to the (n−1).sup.th RC integrator has a reset mechanism responsive to a reset signal output from a reset controller when an input signal overload condition is detected at the input. Upon detecting the overload condition, each of the third RC integrator to the (n−1).sup.th RC integrator is hard reset, the n.sup.th RC integrator is not reset, and a controlled reset is performed on the second RC integrator to recover from saturation caused by the signal overload condition, while maintaining the output signal below the 1% total harmonic distortion (THD) level at or near full power delivery.

Examples of amplifiers and n.sup.th-order loop filters thereof are configured to enable fast and robust recovery from saturation, while limiting signal distortion at or near full power delivery across multiple process and temperature corners. An example n.sup.th-order loop filter comprises n series-coupled resistor-capacitor (RC) integrators. In an example, each of the second RC integrator to the (n−1).sup.th RC integrator has a reset mechanism responsive to a reset signal output from a reset controller when an input signal overload condition is detected at the input. Upon detecting the overload condition, each of the third RC integrator to the (n−1).sup.th RC integrator is hard reset, the n.sup.th RC integrator is not reset, and a controlled reset is performed on the second RC integrator to recover from saturation caused by the signal overload condition, while maintaining the output signal below the 1% total harmonic distortion (THD) level at or near full power delivery.

A system and method for tuning a transistor-based circuit. The system includes a negative impedance converter circuit having a capacitor, a first transistor, and a second transistor. As a current travels through the capacitor, the first transistor and the second transistor each sample voltage at the capacitor and invert the voltage at an input of the negative impedance converter circuit. The negative impedance converter circuit also has a third transistor in series with the capacitor. The third transistor has a base voltage. Changing the base voltage of the third transistor changes the voltage sampled by the first transistor and the second transistor.

A system and method for tuning a transistor-based circuit. The system includes a negative impedance converter circuit having a capacitor, a first transistor, and a second transistor. As a current travels through the capacitor, the first transistor and the second transistor each sample voltage at the capacitor and invert the voltage at an input of the negative impedance converter circuit. The negative impedance converter circuit also has a third transistor in series with the capacitor. The third transistor has a base voltage. Changing the base voltage of the third transistor changes the voltage sampled by the first transistor and the second transistor.

Methods and devices to address body leakage current generation and bias voltage distribution associated with body leakage current in an OFF state of a FET switch stack are disclosed. The devices include charge redistribution arrangements and bridge networks to perform coupling/decoupling to/from the FET switch stack. Detailed structures of such bridge networks are also described.

Methods and devices to address body leakage current generation and bias voltage distribution associated with body leakage current in an OFF state of a FET switch stack are disclosed. The devices include charge redistribution arrangements and bridge networks to perform coupling/decoupling to/from the FET switch stack. Detailed structures of such bridge networks are also described.

According to one embodiment, a coupler includes first to fourth capacitors, first and second inductors, and a first Josephson junction. The first capacitor includes a first capacitor end portion and a first capacitor other-end portion. The first inductor includes a first inductor end portion, and a first inductor other-end portion. The second inductor includes a second inductor end portion, and a second inductor other-end portion. The first Josephson junction includes a first Josephson junction end portion, and a first Josephson junction other-end portion. A space is surrounded with the first inductor, the second inductor, and the first Josephson junction. The third capacitor includes a third capacitor end portion, and a third capacitor other-end portion. The fourth capacitor includes a fourth capacitor end portion, and a fourth capacitor other-end portion.

According to one embodiment, a coupler includes first to fourth capacitors, first and second inductors, and a first Josephson junction. The first capacitor includes a first capacitor end portion and a first capacitor other-end portion. The first inductor includes a first inductor end portion, and a first inductor other-end portion. The second inductor includes a second inductor end portion, and a second inductor other-end portion. The first Josephson junction includes a first Josephson junction end portion, and a first Josephson junction other-end portion. A space is surrounded with the first inductor, the second inductor, and the first Josephson junction. The third capacitor includes a third capacitor end portion, and a third capacitor other-end portion. The fourth capacitor includes a fourth capacitor end portion, and a fourth capacitor other-end portion.

Disclosed is an electromagnetic-circuit co-design approach for massively reconfigurable, multifunctional, and high-speed programmable metasurfaces with integrated chip tiling. The ability to manipulate the incident electromagnetic fields in a dynamically programmable manner and at high speeds using integrated chip tiling approach is also disclosed. The scalable architecture uses electromagnetic-circuit co-design of metasurfaces where each individual subwavelength meta-element is uniquely addressable and programmable. The disclosed device comprises a large array of such meta-elements. The design relies on integrated high frequency switches designed in conjugation with meta-element for massive reconfigurability of incident amplitude and phase. The disclosed chip is multi-functional and can perform beamforming, high speed spatial light modulation, dynamic holographic projections, and wavefront manipulation.