An impedance adjusting circuit includes: a first node coupled to a resistor; a first impedance unit having an impedance value determined based on a first impedance code and coupled between a first voltage terminal and a second node; a first switching unit suitable for electrically connecting the first node and the second node to each other in response to a clock; a first average voltage unit suitable for generating an average voltage of the first node; a first comparison unit suitable for comparing the average voltage of the first node with a first reference voltage to produce a comparison result of the first comparison unit; and a first code generation unit suitable for generating the first impedance code in response to the comparison result of the first comparison unit.

Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for detecting characteristics of an input signal. One aspect includes a first finite input response (FIR) filter, a second FIR filter, and a controller coupled with the first and second FIR filters. The first FIR filter receives an input signal and a first reference signal. The first FIR filter filters the first reference signal to generate a first sinusoidal signal and mixes the first sinusoidal signal and the input signal to generate a first mixed signal. The second FIR filter receives the input signal and a second reference signal. The second FIR filter filters the second reference signal to generate a second sinusoidal signal and mixes the second sinusoidal signal and the input signal to generate a second mixed signal. The controller determines characteristics of the input signal based on the first and second mixed signals.

Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for detecting characteristics of an input signal. One aspect includes a first finite impulse response (FIR) filter, a second FIR filter, and a controller coupled with the first and second FIR filters. The first FIR filter receives an input signal and a first reference signal. The first FIR filter filters the first reference signal to generate a first sinusoidal signal and mixes the first sinusoidal signal and the input signal to generate a first mixed signal. The second FIR filter receives the input signal and a second reference signal. The second FIR filter filters the second reference signal to generate a second sinusoidal signal and mixes the second sinusoidal signal and the input signal to generate a second mixed signal. The controller determines characteristics of the input signal based on the first and second mixed signals.

In accordance with an example, an integrated circuit includes a linear combiner having an input for receiving a signal. The linear combiner also has a plurality of operator circuits for applying weighting factors to the signal, in which a first operator circuit in the plurality of operator circuits performs a first operation on the signal using a first sub-weight of one of the weighting factors to provide a first tile output and a second operator circuit in the plurality of operator circuits performs a second operation on the signal using a second sub-weight of the one of the weighting factors to provide a second tile output. The linear combiner also has an adder having a first input coupled to receive the first tile output and the second tile outputs and providing a combined output.

A low profile two probe load-pull slide screw impedance tuner uses two tuning probes sharing the same slabline; they are inserted diametrically at fixed depth (distance from the center conductor) from both sides into the channel and move only horizontally along the slabline. The tuner does not have adjustable vertical axes controlling the penetration of the probes and its low profile is optimized for on-wafer operations. The carriages holding the probes are moved at high speed along the slabline using linear electric actuators. The S shaped center conductor allows for a neutral zero 50 Ohm state. An efficient de-embedding calibration method serves speeding up the measurement procedure additionally.

Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for detecting characteristics of an input signal. One aspect includes a first finite input response (FIR) filter, a second FIR filter, and a controller coupled with the first and second FIR filters. The first FIR filter receives an input signal and a first reference signal. The first FIR filter filters the first reference signal to generate a first sinusoidal signal and mixes the first sinusoidal signal and the input signal to generate a first mixed signal. The second FIR filter receives the input signal and a second reference signal. The second FIR filter filters the second reference signal to generate a second sinusoidal signal and mixes the second sinusoidal signal and the input signal to generate a second mixed signal. The controller determines characteristics of the input signal based on the first and second mixed signals.

This disclosure relates to a system for mitigating distortion in a signal, including a first calculation circuit configured to determine a bit-cell population available to be activated of a plurality of bit-cells based on a signal strength of an input signal, a second calculation circuit configured to determine a number of bit-cells to be activated based on the signal strength of the input signal, the number of bit-cells to be activated being less than or equal to the bit-cell population, a variable-width dynamic element matching network (variable DEM) configured to activate a first subset of bit-cells of the bit-cell population based on the number of bit-cells to be activated, and one or more fixed-width dynamic element matching networks (fixed DEMs) configured to activate a second subset of bit-cells of the bit-cell population based on the number of bit-cells to be activated.

This disclosure relates to a system for mitigating distortion in a signal, including a plurality of bit-cells, a calculation circuit configured to determine a bit-cell population that is available to be activated for a given clock cycle, a dynamic element matching network configured to activate a subset of bit-cells of the bit-cell population, and a controller configured to control a pattern of activation of the subset of bit-cells of the bit-cell population.

The present invention provides a circuit capable of automatically adjusting impedance thereof having a wide adjustment range and high accuracy by selecting a pull-up code and a pull-down code for obtaining resistances closest to those of a first reference resistor and a second reference resistor, respectively, using a first reference P-code and a second reference P-code, and a first reference N-code and a second reference N-code.