An inverter system for mitigating oscillation of an electric motor that drives a load comprises a torque command generation module for receiving a commanded torque from an operator of a vehicle. A torque damping module is configured to receive the commanded torque and generating a commanded compensating torque to dampen any mechanical oscillation or resonance of the electric motor based on the observed rotational speed of the motor. The torque damping module further comprises a digital filter of order greater than one, a gain adjuster and a limiter.

An inverter system for mitigating oscillation of an electric motor that drives a load comprises a torque command generation module for receiving a commanded torque from an operator of a vehicle. A torque damping module is configured to receive the commanded torque and generating a commanded compensating torque to dampen any mechanical oscillation or resonance of the electric motor based on the observed rotational speed of the motor. The torque damping module further comprises a digital filter of order greater than one, a gain adjuster and a limiter.

A method for updating a stable cuckoo filter used for membership testing of data streams, executed by a processor, is described. The method includes the steps of: performing a first hash on a first element to be inserted into the stable cuckoo filter to determine a first candidate bucket; performing a second hash on a fingerprint of the first element to determine a second candidate bucket; selecting a target candidate bucket from a group consisting of the first candidate bucket and the second candidate bucket; inserting the first element into the target candidate bucket; updating the stable cuckoo filter according to one or more of a random update strategy, an insertion failure update strategy, a scanning strategy, a skip scanning update strategy, a blocked design strategy and a local time-sensitive update strategy; and obtaining an updated stable cuckoo filter.

A method for updating a stable cuckoo filter used for membership testing of data streams, executed by a processor, is described. The method includes the steps of: performing a first hash on a first element to be inserted into the stable cuckoo filter to determine a first candidate bucket; performing a second hash on a fingerprint of the first element to determine a second candidate bucket; selecting a target candidate bucket from a group consisting of the first candidate bucket and the second candidate bucket; inserting the first element into the target candidate bucket; updating the stable cuckoo filter according to one or more of a random update strategy, an insertion failure update strategy, a scanning strategy, a skip scanning update strategy, a blocked design strategy and a local time-sensitive update strategy; and obtaining an updated stable cuckoo filter.

A finite impulse response (FIR) filter includes a plurality of registers. The data input terminal of each register is directly coupled to the input of the FIR filter. A new data value is passed to each register on each clock cycle of a filter clock signal. Only one of the registers processes the data value on each clock cycle. A ring counter is coupled to the registers and determines which register processes the data value on each dock cycle.

A digitally controlled analog filter device. The digitally controlled analog filter device includes one or more digitally controlled analog signal amplifiers. The digitally controlled analog signal amplifiers are configured to have a gain of the digitally controlled analog signal amplifiers controlled by digital signals. The digitally controlled analog filter device further includes one or more analog time delay circuits coupled to signal input nodes of the digitally controlled analog signal amplifiers. The analog time delay circuits are configured to implement an analog signal delay. The digitally controlled analog filter device further includes a digital closed loop control circuit coupled to the digitally controlled analog signal amplifiers to digitally control the gain of the digitally controlled analog signal amplifiers.

A digitally controlled analog filter device. The digitally controlled analog filter device includes one or more digitally controlled analog signal amplifiers. The digitally controlled analog signal amplifiers are configured to have a gain of the digitally controlled analog signal amplifiers controlled by digital signals. The digitally controlled analog filter device further includes one or more analog time delay circuits coupled to signal input nodes of the digitally controlled analog signal amplifiers. The analog time delay circuits are configured to implement an analog signal delay. The digitally controlled analog filter device further includes a digital closed loop control circuit coupled to the digitally controlled analog signal amplifiers to digitally control the gain of the digitally controlled analog signal amplifiers.

The implementation of modal processors, which involve the parallel combination resonant filters, may be costly for applications such as artificial reverberation that can require thousands of modes. In one embodiment, the input signal is decomposed into a plurality of subbands, the outputs of which are downsampled. In each downsampled band, resonant filters are applied at the downsampled sampling rate, and their output is upsampled and filtered to form the band output. In these and other embodiments, a feature of responses of the mode filters have been optimized to minimize an aspect of a residual error after a point in time.

Disclosed are some examples of retimer circuitry, systems and methods. In some implementations, clock data recovery circuitry is coupled between a receiver and a transmitter. The clock data recovery circuitry is configured to: extract a data component from an input data signal associated with the receiver, provide the data component to the transmitter, and generate a phase control signal. Phase interpolator circuitry is coupled with the clock data recovery circuitry. The phase interpolator circuitry includes a phase interpolator configured to: receive the phase control signal, generate, based on the phase control signal, an output clock signal, and provide the output clock signal to the transmitter to track data packets of the data component.

Disclosed are some examples of retimer circuitry, systems and methods. In some implementations, clock data recovery circuitry is coupled between a receiver and a transmitter. The clock data recovery circuitry is configured to: extract a data component from an input data signal associated with the receiver, provide the data component to the transmitter, and generate a phase control signal. Phase interpolator circuitry is coupled with the clock data recovery circuitry. The phase interpolator circuitry includes a phase interpolator configured to: receive the phase control signal, generate, based on the phase control signal, an output clock signal, and provide the output clock signal to the transmitter to track data packets of the data component.