A digital phase shifter includes a plurality of digital phase shift circuit groups in which a plurality of digital phase shift circuits are connected in cascade and one or more bend-type connection units connected between two digital phase shift circuit groups. At least one of the digital phase shift circuits constituting at least one digital phase circuit group is a mitigation circuit that mitigates a distribution of phase shift amounts.

An FIR filter convolutes sampled data obtained by sampling a reception signal with tap coefficients. A phase difference detector detects a phase difference between a synchronization timing of a signal waveform estimated from an output signal of the FIR filter and a sampling timing of the output signal. A tap coefficient adjuster adjusts the tap coefficients so as to reduce the phase difference detected by the phase difference detector and causes the sampling timing of the output signal of the FIR filter to track the synchronization timing.

A phase shifter for altering the phase of a radio frequency signal is disclosed herein. A Lange coupler is used having reflective ports that are coupled to artificial transmission lines. The artificial transmission lines provide a reflection transmission path, the length of which can be determined by digital control lines. Transistors placed along the length of the central trace provide independent paths to ground that serve to shorten the electrical length of the ATL. Accordingly, by selectively turning the transistors on/off, the electrical length of the ATL can be selected and thus the amount of phase delay introduced by the phase shifter.

A phase shifter for altering the phase of a radio frequency signal is disclosed herein. A Lange coupler is used having reflective ports that are coupled to artificial transmission lines. The artificial transmission lines provide a reflection transmission path, the length of which can be determined by digital control lines. Transistors placed along the length of the central trace provide independent paths to ground that serve to shorten the electrical length of the ATL. Accordingly, by selectively turning the transistors on/off, the electrical length of the ATL can be selected and thus the amount of phase delay introduced by the phase shifter.

Aspects of the present disclosure describe systems, methods, and structures including integrated laser systems that employ external chirping structures that may advantageously include phase shifters and/or one or more filters. Further aspects of the present disclosure describe systems, methods, and structures including laser systems that employ external chirping structures that may advantageously include optical phased arrays.

Aspects of the present disclosure describe systems, methods, and structures including integrated laser systems that employ external chirping structures that may advantageously include phase shifters and/or one or more filters. Further aspects of the present disclosure describe systems, methods, and structures including laser systems that employ external chirping structures that may advantageously include optical phased arrays.

A digital phase shifter includes a logic control circuit, at least four current digital-to-analog converters, at least four amplifiers, and a vector summation circuit. The logic control circuit generates four N-bit digital phase shift control signals according to an (N+2)-bit digital control source signal, and respectively inputs the four N-bit digital phase shift control signals to the four current digital-to-analog converters. The four current digital-to-analog converters are respectively connected in series with the four amplifiers, to implement selection and amplification on four orthogonal input signals, and the vector summation circuit synthesizes amplified signals that are output by the four amplifiers, to obtain a signal having a 360 degree () phase shift range.

A digital phase shifter includes a logic control circuit, at least four current digital-to-analog converters, at least four amplifiers, and a vector summation circuit. The logic control circuit generates four N-bit digital phase shift control signals according to an (N+2)-bit digital control source signal, and respectively inputs the four N-bit digital phase shift control signals to the four current digital-to-analog converters. The four current digital-to-analog converters are respectively connected in series with the four amplifiers, to implement selection and amplification on four orthogonal input signals, and the vector summation circuit synthesizes amplified signals that are output by the four amplifiers, to obtain a signal having a 360 degree () phase shift range.

An FIR filter convolutes sampled data obtained by sampling a reception signal with tap coefficients. A phase difference detector detects a phase difference between a synchronization timing of a signal waveform estimated from an output signal of the FIR filter and a sampling timing of the output signal. A tap coefficient adjuster adjusts the tap coefficients so as to reduce the phase difference detected by the phase difference detector and causes the sampling timing of the output signal of the FIR filter to track the synchronization timing.

A delay line is constructed by combining a phase generator and a fabric. The phase generator splits a digital input signal in multiple incrementally delayed versions, which are input to the fabric. The fabric has an array of node filters. Inputs of filters in the first array column are inputs of the fabric. A node filter has a delay element and a cross-coupling element, whose output signals are added or subtracted to form a filter output signal. A node filter in a row is concatenated to the previous filter in the row through its delay element. Inputs of cross-coupling elements are connected to other array rows. Outputs of node filters form the outputs of the fabric. Delay times of delay elements and cross-coupling elements are nominally equal. Drive strengths of cross-coupling elements may be lower than drive strengths of delay elements.