A radio frequency transmitter includes a transmit circuit configured to generate a transmit signal; a receive band rejection filter comprising a capacitor and an inductor resonating with each other to reject a receive frequency band from the transmit signal, wherein a ratio value of a capacitance value of the capacitor to an inductance value of the inductor is within a predetermined range; and a power amplifying circuit configured to amplify the transmit signal through the receive band rejection filter.

Sense amplifiers for use in connection with microelectromechanical system (MEMS) gyroscopes are described. The sense amplifiers may be configured to change the level of a gyroscope signal, i.e., the signal produced by a gyroscope in response to angular motion, to a level suitable for processing circuitry arranged to infer the angular velocity. The sense amplifier may further provide a DC discharge path allowing for discharge of the DC component of the output signal. The DC discharge path may include an anti-aliasing filter and a resistive circuit. The anti-aliasing filter may filter the output signal to maintain the resistive circuit in the linear region. The anti-aliasing filter may be designed with a frequency response such that discrete frequency sub-bands are blocked or at least attenuated. The frequency sub-bands may be tuned to substantially match the gyroscope's resonant frequency and its integer multiples.

An apparatus includes a differential current-to-voltage conversion circuit that includes an input sampling stage circuit, a differential integration and DC signal cancellation stage circuit, and an amplification and accumulator stage circuit. An input common mode voltage of the differential current-to-voltage conversion circuit is independent of an output common mode voltage of the differential current-to-voltage conversion circuit.

A variable capacitor bank includes a conductive housing and a port extending through the housing. An electrical bus is disposed within the conductive housing and coupled to the port. The variable capacitor bank further includes capacitor modules disposed within the housing. Each capacitor module includes a module input electrically coupled to the electrical bus and a switched capacitor branch electrically coupled to the module input, the switched capacitor branch including a capacitor and a switch element in series with the capacitor. In certain implementations, one or more of the capacitor modules may include at least one second switched capacitor branch. The capacitor modules may further include an unswitched, or floor, capacitor that provides a minimum or otherwise known capacitance of the capacitor module. Each capacitor module may further be grounded by being electrically coupled to the conductive housing.

Integrator circuits comprising switched capacitors, non-switched capacitors, and an op amp. One embodiment is directed to an integrator circuit comprising an op amp having an inverting input, a non-inverting input, an inverting output and a non-inverting output, a first sampling capacitor and a first feedback capacitor, and a first non-switched capacitor. The first feedback capacitor is coupled between the inverting input and the non-inverting output of the op amp, and the first non-switched capacitor is coupled between the negative integrator input and the inverting input of the op amp. During a sampling phase, a positive integrator input is coupled to the first sampling capacitor, and during an integration phase, a charge sampled across the first sampling capacitor during the sampling phase is transferred to the first integration capacitor.

The present application provides a window function processing module including an integrating circuit, configured to receive an integrating input signal, the integrating circuit comprising an operational amplifier; an integrating capacitor, coupled to an output terminal and a first input terminal of the operational amplifier; and an adjustable impedance module, coupled between the first input terminal of the operational amplifier and an integrating input terminal of the integrating circuit, wherein the adjustable impedance module is controlled by at least one control signal to adjust an impedance value of the adjustable impedance module; and a control unit, coupled to the integrating circuit, configured to generate the at least one control signal according to a window function, to adjust the integration gain of the integrating circuit, such that the integrating output signal is related to an operation result of the integrating input signal and the window function.

The disclosure provides a circuit that includes an integrator that generates an integrated signal in response to a current signal. A comparator is coupled to the integrator and receives the integrated signal and a primary reference voltage signal. The comparator generates a feedback signal. A switched capacitor network is coupled across the integrator. The feedback signal activates the switched capacitor network.

An apparatus includes a switched-capacitor filter. The switched-capacitor filter includes an integrator and a feedback loop between an output node of the integrator and an input node of the integrator, wherein the feedback loop includes a feedback capacitor, a first switch, and a second switch. The switched-capacitor filter also includes a pre-charge path between the output node of the integrator and the feedback capacitor, wherein the pre-charge path includes a pre-charge buffer and a third switch.

A novel and useful discrete time IIR bandpass filter is disclosed that takes advantage of clock phase reuse thereby leading to significant improvements in filtering, especially stop band rejection in comparison to prior art filters. The bandpass filter of the present invention achieves improved filtering performance without adding any additional clock phases to the circuit. In particular, reuse of the already existing clock phases increases the order and performance of the filter. The invention exploits reuse of the clock phases to provide higher order filtering along with a discrete time IIR filter design which is capable of operating at high frequency. Consequently, much better filtering is achieved and the quality factor of the filter is improved leading to sharper transition bands especially for close-in band blockers in modern 4G/5G receivers.

A loop filter has a first switched-capacitor network and a second switched-capacitor network. The first switched-capacitor network is coupled to an input node of the loop filter. The second switched-capacitor network is coupled to the input node of the loop filter. The input node of the loop filter is arranged to receive an input from a charge pump.