A time register includes: a pair of inputs coupled to a pair of input clocks; a pair of tri-state inverters for producing a pair of level signals; and a pair of outputs coupled to the level signals for producing a pair of output clocks, wherein the tri-state inverters are responsive to a pair of state signals and the pair of input clocks for holding or discharging the level signals.

An equalizer circuit includes an phase-to-phase connectors including an phase-to-phase capacitor and four phase-to-phase switches, four output buffers, and control signal generation circuitry. One terminal of each phase-to-phase switches is connected to one of four connection paths on which four conversion signals being different in phase by 90 are input. The other one terminal of each phase-to-phase switches is connected to the phase-to-phase capacitor. Each output buffer is connected to one of the four connection paths and outputs an output signal. The control signal generation circuitry outputs control signals to control turning-on/off of the respective four phase-to-phase switches. A closing of the first, second, third, and fourth phase-to-phase switches are started from any one of phase-to-phase switches in one of a first ascending circulation and a first descending circulation based on the 4-phase control signals.

The present disclosure relates to an input circuit comprising positive and negative branches, each branch comprising a transistor arranged for receiving an input voltage at its gate terminal and a first fixed voltage at its drain terminal via a first switch characterized in that the source terminal of the transistor in each of the positive branch and the negative branch is connectable via a second switch to a first plate of a first capacitor in the positive branch and of a second capacitor in the negative branch, respectively, with a second plate of the first capacitor and of the second capacitor being connected to a second fixed voltage and the input circuit further being arranged for receiving a first reset voltage on the first plate of the first capacitor in the positive branch and a second reset voltage on the first plate of the second capacitor in the negative branch.

A tracker module is provided that includes a module laminate, an IC chip disposed at the module laminate, and a filter circuit including a plurality of inductors. The IC chip includes at least one switch included in a switched-capacitor circuit and at least one switch included in a supply modulator. The plurality of inductors include a first inductor and a second inductor that are disposed at the module laminate. The first inductor and the second inductor are adjacent to each other. A magnetic flux direction of the first inductor and a magnetic flux direction of the second inductor are perpendicular to each other.

In certain aspects, a system includes a voltage line, a switched-capacitor circuit coupled to the voltage line, and a ripple-cancellation circuit. The ripple-cancellation circuit includes a current mirror having a first branch and a second branch, wherein the second branch of the current mirror is coupled to the voltage line, a switching circuit having a first terminal, a second terminal, and a third terminal, wherein the first terminal of the switching circuit is coupled to the first branch of the current mirror, and the third terminal is coupled to a ground or a reference voltage, and a first capacitor coupled to the second terminal of the switching circuit.

The disclosure provides a circuit that includes an integrator that generates an integrated signal in response to a current signal. A comparator is coupled to the integrator and receives the integrated signal and a primary reference voltage signal. The comparator generates a feedback signal. A switched capacitor network is coupled across the integrator. The feedback signal activates the switched capacitor network.

A system may comprise a high-pass filter having an input for receiving an input signal, an output for generating an output signal, a capacitor coupled between the input and the output, a switched-capacitor resistor coupled between the output and a reference voltage, and control circuitry configured to control the reference voltage to cancel current leakage into a circuit coupled to the output. The input, the output, the capacitor, and the switched-capacitor resistor may be arranged to generate the output signal as a high-pass filtered version of the input signal and the high-pass filter may be configured to operate in a plurality of modes comprising at least a high-impedance mode and a low-impedance mode in which the resistance of the switched-capacitor resistor is significantly smaller than the resistance when in the high-impedance mode.

A tunable filter is described where the frequency response as well as bandwidth and transmission loss characteristics can be dynamically altered, providing improved performance for transceiver front-end tuning applications. The rate of roll-off of the frequency response can be adjusted to improve performance when used in duplexer applications. The tunable filter topology is applicable for both transmit and receive circuits. A method is described where the filter characteristics are adjusted to account for and compensate for the frequency response of the antenna used in a communication system.

In pipelined analog-to-digital converters (ADCs), a passive switched capacitor (PSWC) circuit can be used in a multiplying analog-to-digital converter (MDAC), which generates an analog output being fed to a subsequent stage. Complementary analog input signals are sampled respectively onto first and second capacitors, which are stacked to provide gain. The first capacitor is positioned between a first input switch and an output node of the PSWC circuit, and the second capacitor is positioned between the second input switch and a digital-to-analog converter (DAC) output. The topology advantageously isolates common modes of the complementary analog input signals, the DAC output, and the output of the PSWC circuit. As a result, the topology offers more degrees of freedom in the overall circuit design when stages having the MDAC are cascaded, resulting in pipelined ADCs with a more elegant design with lower noise and lower power consumption.

A charge sharing filter includes a rotating capacitor, and a plurality of elementary filters, each elementary filter comprising: an elementary switch coupled between a first node of the respective elementary filter and a second node of the respective elementary filter; and a history capacitor coupled to the first node of the respective elementary filter, wherein the second nodes of the plurality of elementary filters are interconnected with the rotating capacitor in one interconnecting node.