A circuit for processing an input-signal voltage, and including an input capacitance coupled between an input node of the circuit and a sense node of a comparator; a reference capacitance coupled to the sense node of the comparator; and a common mode switch coupled between the sense node and a reference node of the comparator. The circuit is configured to have the input capacitance set to a reference input voltage while the common mode switch is closed, and the input node set to the input-signal voltage while the common mode switch is open. The reference capacitance includes a plurality of capacitances, at least one of which is provided as a switched capacitance that is selectively controllable to configure the plurality of capacitances. A switched capacitance controller is configured to control the switched capacitance so as to compensate, at the sense node, a comparator offset voltage.

A system may comprise a high-pass filter having an input for receiving an input signal, an output for generating an output signal, a capacitor coupled between the input and the output, a switched-capacitor resistor coupled between the output and a reference voltage, and control circuitry configured to control the reference voltage to cancel current leakage into a circuit coupled to the output. The input, the output, the capacitor, and the switched-capacitor resistor may be arranged to generate the output signal as a high-pass filtered version of the input signal and the high-pass filter may be configured to operate in a plurality of modes comprising at least a high-impedance mode and a low-impedance mode in which the resistance of the switched-capacitor resistor is significantly smaller than the resistance when in the high-impedance mode. A system may include a plurality of processing paths having a first path configured to generate a first digital signal based on an analog input signal and a second path configured to generate a second digital signal based on the analog input signal, the second path having a high-pass filter for filtering the analog input signal prior to the analog input signal being processed by the remainder of the second path, and the high-pass filter having a corner frequency. Control circuitry may be configured to determine frequency-dependent weighted proportions of the first and second digital signals to be combined into an output digital signal based on a characteristic of the analog input signal. Frequency-dependent weighted proportions may be such that the digital output signal includes spectral content of the first digital signal below the corner frequency to account for spectral content of the second digital signal below the corner frequency being filtered. A system may include an input for receiving an input signal, an output for generating an output signal, a capacitor coupled between the input and the output, a variable resistor coupled to the output and having a plurality of modes including a first mode in which the variable resistor has a first resistance and a second mode in which the variable resistor has a second resistance, and control circuitry configured to determine a difference between the input signal and the output signal and switch between modes of the plurality of modes when the difference is less than a predetermined threshold.

A circuit containing a first cascode circuit and a second cascode circuit is proposed. The first circuit and the second cascode circuit are stacked between two power supply terminals. An output signal terminal of the circuit is coupled to a node connecting the first cascode circuit and the second cascode circuit. A first signal path is provided between the first cascode circuit and a common ground terminal and a second signal path is provided between the second cascode circuit and the common ground terminal.

A system may include a ramp generation circuit for generating a ramp waveform and comprising a first passive circuit element having an impedance pertinent to generation of the ramp waveform and a control circuit comprising a second passive circuit element which is impedance-correlated to the first passive circuit element. The control circuit may be configured to use the second passive circuit element to generate a control signal for controlling the ramp generation circuit, such that a correlation between the first passive circuit element and the second passive circuit element substantially cancels physical variations of the first passive circuit element and the second passive circuit element and use a control signal clock for generating the control signal that is related to a ramp generation clock for generating the ramp waveform such that a magnitude of the ramp waveform remains substantially independent of frequency of operation.

An IF filter band-limits an intermediate frequency signal outputted from a mixer. An AFC unit controls the oscillation frequency of a PLL so that the frequency of the intermediate frequency signal is a predetermined frequency. When the AFC unit controls the oscillation frequency of the PLL, a band control unit controls the passing characteristic of the IF filter to the passing characteristic of a wide band, and after the completion of the control, controls the passing characteristic of the IF filter to the passing characteristic of a narrow band. A frequency correction unit refers to a filter information storage unit, and corrects the oscillation frequency controlled by the AFC unit according to the difference between the center frequency of the passband of the passing characteristic of the wide band and the center frequency of the passband of the passing characteristic of the narrow band.

A voltage divider is described. The voltage divider comprises a pair of input nodes for receiving an input signal; a pair of output nodes configured to generate an output signal; a first capacitor having a first terminal coupled to a first output node of the pair of output nodes and a second terminal coupled to a second output node of the pair of output nodes; and a second capacitor having first terminal and a second terminal; a bypass switch having a first terminal coupled to the first terminal of the second capacitor and a second terminal coupled to the second terminal of the second capacitor; and a charge sharing switch coupled to the second terminal of the second capacitor; wherein the bypass switch and the charge sharing switch enable the sharing of charge between the first capacitor and the second capacitor.

A small capacitance compensation network circuit, the first switch module (201) and the second switch (202) module are alternately switched between a switched-off state and a switched-on state, so that the compensation capacitor C3 is charged by the capacitor C1; and the third switch module (203) and the fourth switch module (204) are alternately switched between the switched-off state and the switched-on state, so that the compensation capacitor C3 is discharged to charge the capacitor C2, by controlling the alternate switch-on of the first switch module (201) and the second switch module (202), the third switch module (203) and the fourth switch module (204) causes the deviation of the capacitor C1 and the capacitor C2 to be processed and obtain the error signal. Therefore, the compensation capacitor C3 can be designed to be very small, which facilitates the integration of the integrated circuit, eliminates the need for external compensation capacitors and integrated circuit pins, reduces the system cost, and improves the reliability. Therefore, it is solved the problem that the existing compensation network technology has high cost in the power control circuit and poor reliability in the power supply.

A comparator offset calibration system having a comparator offset evaluator and a switched-capacitor network is disclosed, which is in an analog and digital dual domain structure. The comparator offset evaluator receives digital data from an analog-to-digital conversion module, evaluates an offset of a comparator of the analog-to-digital conversion module based on the received digital data, and outputs an evaluated result. The switched-capacitor network processes the evaluated result to generate a control signal. The analog-to-digital conversion module adjusts the offset of the comparator according to the control signal.

The invention provides an anti-aliasing filter (AAF) for discretization at a sampling period. The AAF may include an operational amplifier having an input terminal and an output terminal, a first capacitor coupled between the input terminal and the output terminal, a second capacitor, and a first switch coupled between the first capacitor and the second capacitor. During a first phase, the first switch may conduct the second capacitor to the first capacitor. During a second phase, the first switch may stop conducting the second capacitor to the first capacitor. The first phase may last for one said sampling period.

Various embodiments relate to delta-sigma loop filters with input feedforward. A delta-sigma loop filter may include a first integrator and a quantizer having an input coupled to an output of the first integrator. The delta-sigma loop filter may further include a first summing node having an output coupled to an input of the first integrator. Further, the delta-sigma loop filter may include a feedforward path from an input of the delta-sigma loop filter to a first input of the first summing node. The delta-sigma loop filter may also include a first feedback path from an output of the quantizer to a second input of the first summing node.