Various embodiments relate to an analog-to-digital converter (ADC). The ADC may include a first channel including a first delta-sigma loop filter and a second channel including a second delta-sigma loop filter. Each of the first delta-sigma loop filter and the second delta-sigma loop filter may include a first integrator and a quantizer having an input coupled to an output of the first integrator. Each of the first delta-sigma loop filter and the second delta-sigma loop filter may also include a first summing node having an output coupled to an input of the first integrator, and a feedforward path from an input of the delta-signal loop filter to a first input of the first summing node. Further, each of the first delta-sigma loop filter and the second delta-sigma loop filter may include a first feedback path from an output of the quantizer to a second input of the first summing node.

This disclosure describes systems, methods, and apparatus for a digital-to-analog (DAC) converter, that can be part of a variable capacitor and/or a match network. The DAC can include a digital input, an analog output, N contributors (e.g., switched capacitors), and an interconnect topology connecting the N contributors, generating a sum of their contributions (e.g., sum of capacitances), and providing the sum to the analog output. The N contributors can form a sub-binary sequence when their contributions to the sum are ordered by average contribution. Also, the gap size between a maximum contribution of one contributor, and a minimum contribution of a subsequent contributor, is less than D, where D is less than or equal to two time a maximum contribution of the first or smallest of the N contributors.

An aspect includes a filtering method including operating a first filter to filter a first input signal to generate a first output signal; operating a second filter to filter a second input signal to generate a second output signal; and selectively coupling at least a portion of the second filter with the first filter to filter a third input signal to generate a third output signal. Another aspect includes a filtering method including operating switching devices to configure a filter with a first set of pole(s); filtering a first input signal to generate a first output signal with the filter configured with the first set of pole(s); operating the switching devices to configure the filter with a second set of poles; and filtering a second input signal to generate a second output signal with the filter configured with the second set of poles.

A method, an apparatus and a device for simultaneously sampling multiples signals and a medium are provided. The method includes: modulating multiple target input signals with CDM, to obtain a single target analog signal; performing ?? modulation on the single target analog signal to obtain a target digital bit stream; demodulating the target digital bit stream to obtain a target demodulated bit stream; and filtering the target demodulated bit stream to obtain multiple target output signals. With the method, the hardware overhead for simultaneous sampling of multiple-channel signals is reduced while ensuring accuracy. Accordingly, the apparatus and the device, and the medium have the above beneficial effects.

Integrator circuits comprising switched capacitors, non-switched capacitors, and an op amp. One embodiment is directed to an integrator circuit comprising an op amp having an inverting input, a non-inverting input, an inverting output and a non-inverting output, a first sampling capacitor and a first feedback capacitor, and a first non-switched capacitor. The first feedback capacitor is coupled between the inverting input and the non-inverting output of the op amp, and the first non-switched capacitor is coupled between the negative integrator input and the inverting input of the op amp. During a sampling phase, a positive integrator input is coupled to the first sampling capacitor, and during an integration phase, a charge sampled across the first sampling capacitor during the sampling phase is transferred to the first integration capacitor.

A receiver may include a time-interleaved charge sampler comprising a charge sampler switch in series with a charge sampler capacitor. The receiver may also include a current buffer configured to drive the time-interleaved charge sampler.

A variable resistor may be coupled between a reference voltage source and components of an integrated circuit to reduce issues relating to thermal noise from a reference voltage signal generated by the reference voltage source. The variable resistor may be set to a low level during a first time period and a high level during a second time period, in which the time periods correspond to a sampling period of a switched-capacitor circuit. The low resistance time period may allow quick settling of an input reference voltage signal, whereas the high resistance time period may reduce a bandwidth of noise on a sampling capacitor coupled to the reference voltage signal. The variable resistor and switched-capacitor network may be used in an analog-to-digital converter (ADC), such as in audio circuits.

A small capacitance compensation network circuit, the first switch module (201) and the second switch (202) module are alternately switched between a switched-off state and a switched-on state, so that the compensation capacitor C3 is charged by the capacitor C1; and the third switch module (203) and the fourth switch module (204) are alternately switched between the switched-off state and the switched-on state, so that the compensation capacitor C3 is discharged to charge the capacitor C2, by controlling the alternate switch-on of the first switch module (201) and the second switch module (202), the third switch module (203) and the fourth switch module (204) causes the deviation of the capacitor C1 and the capacitor C2 to be processed and obtain the error signal. Therefore, the compensation capacitor C3 can be designed to be very small, which facilitates the integration of the integrated circuit, eliminates the need for external compensation capacitors and integrated circuit pins, reduces the system cost, and improves the reliability. Therefore, it is solved the problem that the existing compensation network technology has high cost in the power control circuit and poor reliability in the power supply.

A circuit containing a first cascode circuit and a second cascode circuit is proposed. The first circuit and the second cascode circuit are stacked between two power supply terminals. An output signal terminal of the circuit is coupled to a node connecting the first cascode circuit and the second cascode circuit. A first signal path is provided between the first cascode circuit and a common ground terminal and a second signal path is provided between the second cascode circuit and the common ground terminal.

The invention provides an anti-aliasing filter (AAF) for discretization at a sampling period. The AAF may include an operational amplifier having an input terminal and an output terminal, a first capacitor coupled between the input terminal and the output terminal, a second capacitor, and a first switch coupled between the first capacitor and the second capacitor. During a first phase, the first switch may conduct the second capacitor to the first capacitor. During a second phase, the first switch may stop conducting the second capacitor to the first capacitor. The first phase may last for one said sampling period.