An analog to digital conversion circuit includes an analog to digital converter (ADC) circuit operable to convert an analog signal having an oscillation frequency into a first digital signal having a first data rate frequency, where the analog signal includes a set of pure tone components. The analog to digital conversion circuit further includes a digital decimation filtering circuit operable to convert the first digital signal into a second digital signal having a second data rate frequency. The analog to digital conversion circuit further includes a digital bandpass filter (BPF) circuit operable to convert the second digital signal into an outbound digital signal having a third data rate frequency, where the digital bandpass filter circuit is set to produce a bandpass region approximately centered at the oscillation frequency of the analog signal and having a bandwidth tuned for filtering a pure tone.

An analog to digital conversion circuit includes an analog to digital converter (ADC) circuit operable to convert an analog signal having an oscillation frequency into a first digital signal having a first data rate frequency, where the analog signal includes a set of pure tone components. The analog to digital conversion circuit further includes a digital decimation filtering circuit operable to convert the first digital signal into a second digital signal having a second data rate frequency. The analog to digital conversion circuit further includes a digital bandpass filter (BPF) circuit operable to convert the second digital signal into an outbound digital signal having a third data rate frequency, where the digital bandpass filter circuit is set to produce a bandpass region approximately centered at the oscillation frequency of the analog signal and having a bandwidth tuned for filtering a pure tone.

An analog to digital conversion circuit includes an analog to digital converter (ADC) circuit operable to convert an analog signal having an oscillation frequency into a first digital signal having a first data rate frequency, where the analog signal includes a set of pure tone components. The analog to digital conversion circuit further includes a digital decimation filtering circuit operable to convert the first digital signal into a second digital signal having a second data rate frequency. The analog to digital conversion circuit further includes a digital bandpass filter (BPF) circuit operable to convert the second digital signal into an outbound digital signal having a third data rate frequency, where the digital bandpass filter circuit is set to produce a bandpass region approximately centered at the oscillation frequency of the analog signal and having a bandwidth tuned for filtering a pure tone.

A confined data communication system includes a reference generation circuit operable to produce one or more analog reference signals, an analog to digital converter circuit operable to process an analog signal to produce a digital representative signal, a digital filtering circuit operable to filter the digital representative signal to produce an affect value, a data processing module operable to interpret the affect value to produce processed output data, and a processing module operable to set frequency and waveform for each of the one or more analog reference signals, set digital filtering parameters for the digital filtering circuit, set a sampling rate for the analog to digital converter circuit, and set data interpretation parameters for the data processing module.

A digital decimation filtering circuit of an analog to digital conversion circuit includes an n-tap anti-aliasing filter operable to receive a 1-bit analog to digital converter (ADC) output signal at an oversampling rate and filter the 1-bit ADC output signal to remove frequencies higher than a selected cut-off frequency to produce an n-bit filtered signal at a first data output rate. The digital decimation filtering circuit further includes a decimator operable to receive the n-bit filtered signal at the first data output rate, decimate the n-bit filtered signal by a decimation factor to produce a set of output signals, and sum the set of outputs to produce a decimated signal at a second data output rate. The first data output rate is greater than the second data output rate.

A digital control circuitry for a MEMS gyroscope is provided. The digital control circuitry comprises a digital primary loop circuitry configured to process a digitized primary signal, a digital secondary loop circuitry configured to process a digitized secondary signal and a digital phase shifting filter circuitry configured to generate two phase shifted demodulation signals from the digitized primary signal. The digital secondary loop is configured to demodulate the digitized secondary signal using the two phase shifted demodulation signals.

A data sensing circuit includes one or more drive sense circuits operably coupled to a plurality of data sources. The one or more drive sense circuits produces a plurality of digital sense signals regarding the plurality of data sources at an oversampling rate. The data sensing circuit further includes a digital filtering circuit operably coupled to receive, in parallel, at least some of the plurality of digital sense signals and generate, in a serial manner, a plurality of affect values from the least some of the plurality of digital sense signals.

In order to process a subband signal of a plurality of real subband signals which are a representation of a real discrete-time signal generated by an analysis filter bank, a weighter for weighting a subband signal by a weighting factor determined for the subband signal is provided to obtain a weighted subband signal. In addition, a correction term is calculated by a correction term determiner, the correction term determiner being implemented to calculate the correction term using at least one other subband signal and using another weighting factor provided for the other subband signal, the two weighting factors differing. The correction term is then combined with the weighted subband signal to obtain a corrected subband signal, resulting in reduced aliasing, even if subband signals are weighted to a different extent.

Certain aspects of the present disclosure provide circuits for generating high accuracy millimeter wave or radio frequency (RF) wideband in-phase (I) and quadrature (Q) oscillating signals having acceptable amplitude and phase mismatch over process, voltage, and temperature (PVT) variations with reduced cost, area, and power consumption. In one example apparatus, a polyphase filter having a first stage and a second stage is provided. Each stage comprises resistive elements and capacitive elements. Certain aspects of the present disclosure provide for intentional resistive and/or capacitive value mismatch between the resistive or capacitive values of one or multiple stages such that the phase mismatch between the resulting I and Q signals may be reduced without degrading the amplitude mismatch. Certain aspects of the present disclosure provide for replacing the resistive elements in at least one stage with transistors operating in the triode region, where the on-resistance is controlled by a feedback network.

An analog to digital conversion circuit of a touch screen computing device includes a plurality of analog to digital converter circuits operable to convert a plurality of analog signals into a plurality of digital signals at an oversampling rate, a digital decimation filtering module operable to convert the plurality of digital signals into a plurality of digital filtered signals at a first output rate, a coefficient processor operable to generate real component coefficients and imaginary component coefficients of a filtering function at a plurality of frequencies, a first bandpass filter circuit operable to produce first affect values at known frequencies of the plurality of frequencies, and a second bandpass filter circuit operable to produce second affect values at selected frequencies of the plurality of frequencies.