An improved switchable capacitor array comprises a plurality of n2 capacitor units, each comprising a capacitor with a capacitance and a switch unit. The capacitor units are electrically connected in series. Equidistantly spaced impedance values can be obtained if the values of the capacitances are chosen properly.

A tunable inductor arrangeable on a chip or substrate comprises a first winding part connected at one end to a first input of the tunable inductor arrangement, a second winding part connected at one end to the other end of the first winding part, a third winding part connected at one end to a second input of the tunable inductor arrangement, a fourth winding part connected at one end to the other end of the third winding part, and a switch arrangement arranged. The switch arrangement tunes the tunable inductor by selectively connecting the first and fourth winding parts in parallel and the second and third winding parts in parallel, with the parallel couplings in series between the first and second inputs, or connecting the first, second, fourth and third winding parts in series between the first and second inputs. Corresponding transceivers, communication devices, methods and computer programs are disclosed.

Methods and devices providing Positive Logic biasing schemes for use in a digitally tuning capacitor in an integrated circuit device are described. The described methods can be used in integrated circuits with stringent requirements in terms of switching time, power handling, noise sensitivity and power consumption. The described devices include DC blocking capacitors arranged in series with stacked switches coupled to RF nodes. The stacked FET switches receive non-negative supply voltages through their drains and gates during the ON and OFF states to adjust the capacitance between the two nodes.

A radio-frequency impedance tuner can include first node and second nodes, a first series path, a second series path, and an inductance path, each between the first node and the second node and including a switch to allow the path to couple or uncouple the first and second nodes. Each series path can be configured to allow a substantially continuous flow of a direct current between the first node and the second node when coupled. The tuner can further include a shunt path with a switch to allow coupling or uncoupling of the second node and ground. The tuner can further include a switchable grounding path implemented along the inductance path and configured to allow the inductance path to function as a series inductance path between the first and second nodes, or as a shunt inductance path between the ground and a node along the inductance path.

A radio-frequency impedance tuner can include first node and second nodes, a first series path, a second series path, and an inductance path, each between the first node and the second node and including a switch to allow the path to couple or uncouple the first and second nodes. Each series path can be configured to allow a substantially continuous flow of a direct current between the first node and the second node when coupled. The tuner can further include a shunt path with a switch to allow coupling or uncoupling of the second node and ground. The tuner can further include a switchable grounding path implemented along the inductance path and configured to allow the inductance path to function as a series inductance path between the first and second nodes, or as a shunt inductance path between the ground and a node along the inductance path.

Switched capacitor radio frequency receiver front-ends are provided, comprising: a plurality of banks, each comprising: a first switch connected to a RF input signal; a sampling capacitor connected to the first switch and to ground; a second switch connected in parallel to the sampling capacitor; and a Gm cell coupled to the sampling capacitor and an output; wherein: the output of the Gm cell of each of the plurality on banks are coupled together; and the first switch and the second switch are controlled by a multi-phase signal that causes, for each of the plurality of banks, the first switch to be turned ON at a first point in time and the second switch to be turned ON at a second point in time, wherein the first point in time for a first bank is not the same as the first point in time for a second bank.

Switched capacitor radio frequency receiver front-ends are provided, comprising: a plurality of banks, each comprising: a first switch connected to a RF input signal; a sampling capacitor connected to the first switch and to ground; a second switch connected in parallel to the sampling capacitor; and a Gm cell coupled to the sampling capacitor and an output; wherein: the output of the Gm cell of each of the plurality on banks are coupled together; and the first switch and the second switch are controlled by a multi-phase signal that causes, for each of the plurality of banks, the first switch to be turned ON at a first point in time and the second switch to be turned ON at a second point in time, wherein the first point in time for a first bank is not the same as the first point in time for a second bank.

Methods and apparatus that support controlled transmission and directional reception of RTS and/or CTS messages, are described. Controlled transmission may include transmitting a same RTS message multiple times in the same direction and/or transmitting an RTS message with a length that is multiple times longer than a standard RTS message. In an aspect, a receiver may determine spatial directions of a plurality of transmitters including a first transmitter and at least one other transmitter, and may perform a beam sweep in the determined spatial directions for receiving one or more RTS messages. A transmitter may determine that a receiver is to perform a beam sweep in K different spatial directions, and may transmit a same RTS message for a data transmission K times in the same direction or an RTS message with a length approximately K times longer than a standard RTS message, during a duration of the beam sweep.

Methods and devices providing Positive Logic biasing schemes for use in a digitally tuning capacitor in an integrated circuit device are described. The described methods can be used in integrated circuits with stringent requirements in terms of switching time, power handling, noise sensitivity and power consumption. The described devices include DC blocking capacitors arranged in series with stacked switches coupled to RF nodes. The stacked FET switches receive non-negative supply voltages through their drains and gates during the ON and OFF states to adjust the capacitance between the two nodes.

Methods and devices providing Positive Logic biasing schemes for use in a digitally tuning capacitor in an integrated circuit device are described. The described methods can be used in integrated circuits with stringent requirements in terms of switching time, power handling, noise sensitivity and power consumption. The described devices include DC blocking capacitors arranged in series with stacked switches coupled to RF nodes. The stacked FET switches receive non-negative supply voltages through their drains and gates during the ON and OFF states to adjust the capacitance between the two nodes.