Methods and devices providing Positive Logic biasing schemes for use in a digitally tuning capacitor in an integrated circuit device are described. The described methods can be used in integrated circuits with stringent requirements in terms of switching time, power handling, noise sensitivity and power consumption. The described devices include DC blocking capacitors arranged in series with stacked switches coupled to RF nodes. The stacked FET switches receive non-negative supply voltages through their drains and gates during the ON and OFF states to adjust the capacitance between the two nodes.

A biasing circuit for biasing a switching transistor, wherein the switching transistor is used for switching a respective capacitor cell into/out of a capacitor array, wherein the capacitor array comprises one or more such capacitor cells, and wherein the capacitor array is coupled in parallel with a primary inductor to form an inductive/capacitive tank. The biasing circuit comprises a secondary inductor which is inductively coupled to the primary inductor, the secondary inductor configured to provide a bias signal for biasing the switching transistor.

A network element (200) of a cable television (CATV) network, comprising an input (204) for upstream signal transmission; at least two diplex filters (210, 212, 214) configured to be connected to said input (204), a first diplex filter (210) comprising a bandpass filter for a first upstream frequency band and a second diplex filter (212) comprising a bandpass filter for a second upstream frequency band; a switch (208) for connecting one of said at least two diplex filters to said input; wherein the network element is configured to be remotely controlled by a headend of the CATV network for selecting the diplex filter.

A network element (200) of a cable television (CATV) network, comprising an input (204) for upstream signal transmission; at least two diplex filters (210, 212, 214) configured to be connected to said input (204), a first diplex filter (210) comprising a bandpass filter for a first upstream frequency band and a second diplex filter (212) comprising a bandpass filter for a second upstream frequency band; a switch (208) for connecting one of said at least two diplex filters to said input; wherein the network element is configured to be remotely controlled by a headend of the CATV network for selecting the diplex filter.

Disclosed are a wireless power system including a self-regulation rectifier and a communication method thereof. The wireless power system according to an embodiment includes a reception resonator which magnetically resonates with a wireless power transfer unit through a reception antenna, a self-regulation rectifier which rectifies a power signal in a form of an alternating current (AC) received from the reception resonator into a power signal in a form of a direct current (DC) and self-regulates a rectifier output voltage without a separate power converter, and a frequency adjuster which changes a resonance frequency of the reception resonator for in-band communication with the wireless power transfer unit, wherein a reception antenna current is changed according to a change in the resonant frequency, and the reception resonator transmits a communication signal to the wireless power transfer unit through induction of the changed reception antenna current.

A voltage controlled oscillator (VCO) is disclosed to provide reduced phase noise at higher operating frequencies. A buffer-first VCO configured according to an embodiment includes multiple VCO core circuits configured to provide synchronously tuned oscillator signals. Each VCO core circuit is coupled to a summing node through a buffer circuit that generates uncorrelated phase noise such that the summing node provides a summation output of the oscillator signals with reduced phase noise. A multiplexer-less VCO configured according to an embodiment includes multiple buffer-first VCO circuits configured to provide oscillator signals covering a range of frequencies. Each buffer-first VCO circuit is controlled or selected by an enable signal. Buffer circuits are configured to select one of the buffer-first VCO circuits for coupling to a transmission line during a given time period based on the enable signal. The transmission line is terminated in a matched impedance at each end of the line.

A multiport RF switch assembly with integrated impedance tuning capability is described that provides a single RFIC solution to switch between transmit and receive paths in a communication system. Dynamic tuning is integrated into each switch sub-assembly to provide the capability to impedance match antennas or other components connected to the multiport switch. The tuning function at the switch can be used to shape the antenna response to provide better filtering at the switch/RF front-end (RFFE) interface to allow for reduced filtering requirements in the RFFE. Memory is designed into the multiport switch assembly, allowing for a look-up table or other data to reside with the switch and tuning circuit. The resident memory will result in easier integration of the tunable switch assembly into communication systems.

A tunable inductor arrangeable on a chip or substrate comprises a first winding part connected at one end to a first input of the tunable inductor arrangement, a second winding part connected at one end to the other end of the first winding part, a third winding part connected at one end to a second input of the tunable inductor arrangement, a fourth winding part connected at one end to the other end of the third winding part, and a switch arrangement arranged. The switch arrangement tunes the tunable inductor by selectively connecting the first and fourth winding parts in parallel and the second and third winding parts in parallel, with the parallel couplings in series between the first and second inputs, or connecting the first, second, fourth and third winding parts in series between the first and second inputs. Corresponding transceivers, communication devices, methods and computer programs are disclosed.

Methods and devices providing Positive Logic biasing schemes for use in a digitally tuning capacitor in an integrated circuit device are described. The described methods can be used in integrated circuits with stringent requirements in terms of switching time, power handling, noise sensitivity and power consumption. The described devices include DC blocking capacitors arranged in series with stacked switches coupled to RF nodes. The stacked FET switches receive non-negative supply voltages through their drains and gates during the ON and OFF states to adjust the capacitance between the two nodes.

Methods and devices providing Positive Logic biasing schemes for use in a digitally tuning capacitor in an integrated circuit device are described. The described methods can be used in integrated circuits with stringent requirements in terms of switching time, power handling, noise sensitivity and power consumption. The described devices include DC blocking capacitors arranged in series with stacked switches coupled to RF nodes. The stacked FET switches receive non-negative supply voltages through their drains and gates during the ON and OFF states to adjust the capacitance between the two nodes.