A circuit and method are provided. The method couples a first bias signal to a first internal node and a second internal node via a first resistor and a second resistor, respectively, couples a second bias signal to a third internal node and a fourth internal node via a third resistor and a fourth resistor, respectively. The method further couples the first internal node to the second internal node via a switch of a first type controlled by a first control signal, couples the third internal node to the fourth internal node via a switch of a second type controlled by a second control signal, wherein the second control signal is an inversion of the first control signal, couples a first terminal to the first internal node and the third internal node via a first capacitor and a third capacitor, respectively; and couples a second terminal to the second internal node and the fourth internal node via a second capacitor and a fourth capacitor, respectively.

A circuit and method are provided. The method couples a first bias signal to a first internal node and a second internal node via a first resistor and a second resistor, respectively, couples a second bias signal to a third internal node and a fourth internal node via a third resistor and a fourth resistor, respectively. The method further couples the first internal node to the second internal node via a switch of a first type controlled by a first control signal, couples the third internal node to the fourth internal node via a switch of a second type controlled by a second control signal, wherein the second control signal is an inversion of the first control signal, couples a first terminal to the first internal node and the third internal node via a first capacitor and a third capacitor, respectively; and couples a second terminal to the second internal node and the fourth internal node via a second capacitor and a fourth capacitor, respectively.

Provided is a gate drive circuit and a gate drive system, with which current unevenness among power devices connected in parallel can be reduced more. A gate drive circuit includes: an objective waveform generation unit configured to generate an objective waveform; a drive waveform generation unit configured to generate a drive waveform from the objective waveform, by referring to on-timing set information and off-timing set information; a drive control unit configured to drive the power device to turn the power device on/off, based on the drive waveform; a state detection unit configured to detect the state of the power device; a predicted waveform generation unit configured to generate a predicted waveform of a voltage; and an update unit configured to update the on-timing set information and the off-timing set information, based on the result of the state detection and the result of comparison to the predicted waveform.

Provided is a gate drive circuit and a gate drive system, with which current unevenness among power devices connected in parallel can be reduced more. A gate drive circuit includes: an objective waveform generation unit configured to generate an objective waveform; a drive waveform generation unit configured to generate a drive waveform from the objective waveform, by referring to on-timing set information and off-timing set information; a drive control unit configured to drive the power device to turn the power device on/off, based on the drive waveform; a state detection unit configured to detect the state of the power device; a predicted waveform generation unit configured to generate a predicted waveform of a voltage; and an update unit configured to update the on-timing set information and the off-timing set information, based on the result of the state detection and the result of comparison to the predicted waveform.

A circuit and method are provided. The method couples a first bias signal to a first internal node via a first resistor, couples a second bias signal to a second internal node via a second resistor, couples the first internal node to a ground node via a N-type switch, couples the second internal node to a power supply node via a P-type switch. The method further couples the first internal node to the second internal node via a transmission gate, couples a terminal to the first internal node via a first capacitor, and couples the terminal to the second internal node via a second capacitor.

A circuit and method are provided. The method couples a first bias signal to a first internal node via a first resistor, couples a second bias signal to a second internal node via a second resistor, couples the first internal node to a ground node via a N-type switch, couples the second internal node to a power supply node via a P-type switch. The method further couples the first internal node to the second internal node via a transmission gate, couples a terminal to the first internal node via a first capacitor, and couples the terminal to the second internal node via a second capacitor.

An input/output (I/O) circuit may be provided. The I/O circuit may include an input control circuit and an output control circuit. The input control circuit may be configured to apply a stress to a transmission path based on an input signal while in a test mode and buffer the input signal using a drivability changed by the stress applied to the transmission path to generate first and second transmission signals while in a normal mode after the test mode. The output control circuit may be configured to drive and output an output signal according to the first and second transmission signals based on a test mode signal.

An input/output (I/O) circuit may be provided. The I/O circuit may include an input control circuit and an output control circuit. The input control circuit may be configured to apply a stress to a transmission path based on an input signal while in a test mode and buffer the input signal using a drivability changed by the stress applied to the transmission path to generate first and second transmission signals while in a normal mode after the test mode. The output control circuit may be configured to drive and output an output signal according to the first and second transmission signals based on a test mode signal.

A method of adaptively operating a transmit detection circuit is presented. The method includes powering the transmit detection circuit with a capacitor charged by an LDO; receiving a digital ping signal from a transmitter; receiving a clock signal from a local oscillator; updating a register to accommodate timing of the digital ping signal; and generating a signal indicating whether the transmitter is present.

A method of adaptively operating a transmit detection circuit is presented. The method includes powering the transmit detection circuit with a capacitor charged by an LDO; receiving a digital ping signal from a transmitter; receiving a clock signal from a local oscillator; updating a register to accommodate timing of the digital ping signal; and generating a signal indicating whether the transmitter is present.