Random number generator (GL) comprising adjustable speed ring oscillators (GPRS, GPRS′), which have outputs (o-GPRS, o-GPRS′) connected to inputs (i1-UM, i2-UM) of a metastability circuit (UM) and inputs (i1-DF, i2-DF) of a phase detector (DF), which outputs (o-UM, o-DF) are connected to inputs (r-US′, i-US′) of a control circuit (US′), having output (o-US′) connected to control inputs (s-GPRS, s-GPRS′) of the adjustable speed ring oscillators (GPRS, GPRS′). The outputs (o-UM, o-DF) of the metastability circuit (UM) and the phase detector (DF) are being outputs (o-GL, o2-GL) of the random number generator (GL).

Random number generator (GL) comprising adjustable speed ring oscillators (GPRS, GPRS′), which have outputs (o-GPRS, o-GPRS′) connected to inputs (i1-UM, i2-UM) of a metastability circuit (UM) and inputs (i1-DF, i2-DF) of a phase detector (DF), which outputs (o-UM, o-DF) are connected to inputs (r-US′, i-US′) of a control circuit (US′), having output (o-US′) connected to control inputs (s-GPRS, s-GPRS′) of the adjustable speed ring oscillators (GPRS, GPRS′). The outputs (o-UM, o-DF) of the metastability circuit (UM) and the phase detector (DF) are being outputs (o-GL, o2-GL) of the random number generator (GL).

A method, comprising: providing an electrical energy source having a specified amount of electrical energy; connecting an array comprising n magnetic tunnel junctions (MTJ) in parallel to said electrical energy source, wherein each of said MTJs is at a high resistance initial state; discharging said specified energy amount through said MTJs, thereby causing a random subset of said MTJs to switch to a lower resistance state; determining a post-discharging resistance state of each of the MTJs; and assigning a logical state to each of said MTJs corresponding to said resistance state of said MTJ.

A random number generator circuit includes a noise source capable of providing a noise signal that varies randomly; and a circuit for extracting the noise signal including an edge detector configured to produce from the noise signal an analogue signal including voltage pulses, each voltage pulse corresponding to a rising or falling edge of the noise signal, and an analogue-to-digital converter configured to generate a random bit sequence from the analogue signal.

A random number generator circuit includes a noise source capable of providing a noise signal that varies randomly; and a circuit for extracting the noise signal including an edge detector configured to produce from the noise signal an analogue signal including voltage pulses, each voltage pulse corresponding to a rising or falling edge of the noise signal, and an analogue-to-digital converter configured to generate a random bit sequence from the analogue signal.

A clock synthesis circuit and method provides for precision controlling and programming a selected number of clock pulses (or simply “clocks”) fitted within time periods between two consecutive pulses of a so-called system heartbeat (SHB) timing signal. The disclosed embodiments have applicability in light emitting diode (LED) display driver integrated circuits (ICs) and, more generally, digital circuits including computer processors, microcontrollers, logic devices such as field-programmable gate arrays (FP-GA), and other logic circuitry.

A clock synthesis circuit and method provides for precision controlling and programming a selected number of clock pulses (or simply “clocks”) fitted within time periods between two consecutive pulses of a so-called system heartbeat (SHB) timing signal. The disclosed embodiments have applicability in light emitting diode (LED) display driver integrated circuits (ICs) and, more generally, digital circuits including computer processors, microcontrollers, logic devices such as field-programmable gate arrays (FP-GA), and other logic circuitry.

Provided are a random number generating device and a method of operating the same. The random number generating device includes a source detector, a pulse generator, a counter, and a verification circuit. The source detector detects particles emitted from a source to generate a detection signal. The pulse generator generates pulses corresponding to the detected particles, based on the detection signal. The counter measures time intervals among the pulses and generates binary count values respectively corresponding to the time intervals. The verification circuit determines an output of the binary count values, based on the number of 0 values and the number of 1 values included in the binary count values.

A random bit generator includes a voltage source, a bit data cell, and a sensing control circuit. The voltage source provides a scan voltage during enroll operations. The data cell includes a first transistor and a second transistor. The first transistor has a first terminal coupled to a first bit line, a second terminal coupled to the voltage source, and a control terminal. The second transistor has a first terminal coupled to a second bit line, a second terminal coupled to the voltage source, and a control terminal. The sensing control circuit is coupled to the first bit line and the second bit line, and outputs a random bit data according to currents generated through the first transistor and the second transistor during an enroll operation of the bit data cell.

A random bit generator includes a voltage source, a bit data cell, and a sensing control circuit. The voltage source provides a scan voltage during enroll operations. The data cell includes a first transistor and a second transistor. The first transistor has a first terminal coupled to a first bit line, a second terminal coupled to the voltage source, and a control terminal. The second transistor has a first terminal coupled to a second bit line, a second terminal coupled to the voltage source, and a control terminal. The sensing control circuit is coupled to the first bit line and the second bit line, and outputs a random bit data according to currents generated through the first transistor and the second transistor during an enroll operation of the bit data cell.