An apparatus includes a carry chain circuit and a detector circuit. The carry chain circuit includes a plurality of stages. Each stage of the plurality of stages includes a plurality of lookup table elements coupled in sequence. The carry chain circuit propagates a clock signal through the plurality of lookup table elements of the plurality of stages. The detector circuit determines, based on a value of the clock signal stored by a final lookup table element of each stage of the plurality of stages, which stage of the plurality stages contains an edge of the clock signal. The detector circuit then outputs a zero if the determined stage is assigned to a first group of the plurality of stages and a one if the determined stage is assigned to a second group of the plurality of stages.

An apparatus includes a carry chain circuit and a detector circuit. The carry chain circuit includes a plurality of stages. Each stage of the plurality of stages includes a plurality of lookup table elements coupled in sequence. The carry chain circuit propagates a clock signal through the plurality of lookup table elements of the plurality of stages. The detector circuit determines, based on a value of the clock signal stored by a final lookup table element of each stage of the plurality of stages, which stage of the plurality stages contains an edge of the clock signal. The detector circuit then outputs a zero if the determined stage is assigned to a first group of the plurality of stages and a one if the determined stage is assigned to a second group of the plurality of stages.

A random number generator comprising resistive random-access memory (RRAM) devices including: a first electrode; a second electrode; a third electrode located between the first and second electrode; at least one electrically insulating layer separating the first electrode and the second electrode from the third electrode, wherein the at least one electrically insulating layer has a substantially uniform thickness; a first filament that is current conducting and extends through the at least one electrically insulating layer; a second filament is located in the at least one electrically insulating layer and does not extend through the at least one electrically insulating layer; a voltage source configured to apply voltage to at least one of the first electrode and the second electrode; and a voltage sensor configured to sense voltage of the third electrode in order to determine which one of the first filament or the second filament is more resistive.

A random number generator comprising resistive random-access memory (RRAM) devices including: a first electrode; a second electrode; a third electrode located between the first and second electrode; at least one electrically insulating layer separating the first electrode and the second electrode from the third electrode, wherein the at least one electrically insulating layer has a substantially uniform thickness; a first filament that is current conducting and extends through the at least one electrically insulating layer; a second filament is located in the at least one electrically insulating layer and does not extend through the at least one electrically insulating layer; a voltage source configured to apply voltage to at least one of the first electrode and the second electrode; and a voltage sensor configured to sense voltage of the third electrode in order to determine which one of the first filament or the second filament is more resistive.

An apparatus for forming wideband pseudo random noise signals includes a set of channels each comprising an NCO having a controlled frequency and phase and a PRN code generator, the NCO generating a strobe that is output to the PRN code generator. The PRN code generator forms a new sequence element of +1 or −1 in response to the strobe. The apparatus also comprises a first modulator having a plurality of weight coefficients, a plurality of multipliers each multiplying one of the weight coefficients, an adder outputting a sum of the plurality of multipliers output signals, and a mixer with a quadrature output signal multiplying the adder's output by sine and cosine of a low intermediate frequency. The apparatus also includes a processor controlling the set of channels, a transceiver module to receive and/or transmit quadrature signals, and an interface connecting the output of the mixer and the transceiver module.

An apparatus for forming wideband pseudo random noise signals includes a set of channels each comprising an NCO having a controlled frequency and phase and a PRN code generator, the NCO generating a strobe that is output to the PRN code generator. The PRN code generator forms a new sequence element of +1 or −1 in response to the strobe. The apparatus also comprises a first modulator having a plurality of weight coefficients, a plurality of multipliers each multiplying one of the weight coefficients, an adder outputting a sum of the plurality of multipliers output signals, and a mixer with a quadrature output signal multiplying the adder's output by sine and cosine of a low intermediate frequency. The apparatus also includes a processor controlling the set of channels, a transceiver module to receive and/or transmit quadrature signals, and an interface connecting the output of the mixer and the transceiver module.

A spread spectrum clock generation device that may reduce electromagnetic interference (EMI) includes: a first comparator configured to compare an input signal with a first reference voltage and output a first comparison signal; a second comparator configured to compare the input signal with a second reference voltage and output a second comparison signal; a latch configured to receive the first and second comparison signals as inputs and output an output signal; and a delaying circuit configured to generate the input signal by delaying the output signal to have a different delay time for each time interval.

A true random-number generator generating a random variable is provided. A first delay circuit delays an input signal to generate a first delayed signal. A second delay circuit delays the first delayed signal to generate a second delayed signal. A first sampling circuit samples the input signal according to a clock signal to generate a first sampled signal. A second sampling circuit samples the first delayed signal according to the clock signal to generate a second sampled signal. A third sampling circuit samples the second delayed signal according to the clock signal to generate a third sampled signal. An operational circuit generates the random variable and adjusts a count value according to the first sampled signal, the second sampled signal, and the third sampled signal. The operational circuit adjusts the clock signal according to the count value.

A tunable true random number generator (TTRNG) apparatus includes a clock pulse source; a logic voltage source; an output terminal; a ground terminal; and a plurality of transistors that are connected between the clock pulse source, the logic voltage source, the output terminal, and the ground terminal. Also included are resistive memory cells that are connected with the plurality of transistors and at least one of the logic voltage source and the ground terminal. The plurality of transistors are connected such that, at each clock pulse, the plurality of transistors deliver either logic voltage “1” or ground voltage “0” to the output terminal. The resistive memory cells are connected such that a ones probability of the plurality of transistors delivering “1” to the output terminal can be adjusted by changing the resistances of the resistive memory cells.

A tunable true random number generator (TTRNG) apparatus includes a clock pulse source; a logic voltage source; an output terminal; a ground terminal; and a plurality of transistors that are connected between the clock pulse source, the logic voltage source, the output terminal, and the ground terminal. Also included are resistive memory cells that are connected with the plurality of transistors and at least one of the logic voltage source and the ground terminal. The plurality of transistors are connected such that, at each clock pulse, the plurality of transistors deliver either logic voltage “1” or ground voltage “0” to the output terminal. The resistive memory cells are connected such that a ones probability of the plurality of transistors delivering “1” to the output terminal can be adjusted by changing the resistances of the resistive memory cells.