A memory controller for controlling an operation of a semiconductor memory device including a memory block including a plurality of sub-blocks. The memory controller includes a randomizer. The randomizer includes: seed table storage configured to store a plurality of seed tables respectively corresponding to the plurality of sub-blocks, and to generate a seed, based on sub-block information of received original data; a random sequence generator configured to generate a random sequence, based on the seed generated by the seed table storage; and an operating component configured to generate random data, based on the random sequence and the original data.

A memory controller for controlling an operation of a semiconductor memory device including a memory block including a plurality of sub-blocks. The memory controller includes a randomizer. The randomizer includes: seed table storage configured to store a plurality of seed tables respectively corresponding to the plurality of sub-blocks, and to generate a seed, based on sub-block information of received original data; a random sequence generator configured to generate a random sequence, based on the seed generated by the seed table storage; and an operating component configured to generate random data, based on the random sequence and the original data.

Embodiments provide a true random number generator. The true random number generator may include a first ring oscillator having a first frequency, a second ring oscillator having a second frequency, a third ring oscillator having a third frequency, and a capacitor connected between the second ring oscillator and the third ring oscillator to provide a capacitive coupling therebetween. The second frequency is lower than the first frequency, and the third frequency is lower than the second frequency. The true random number generator may further include a D-type flip-flop having a data input connected to an output of the first ring oscillator and having a clock input connected to an output of the third ring oscillator, wherein the D-type flip-flop is configured to generate an output signal representing a sequence of random numbers.

A digital calibration method, a device, and a true random number generator circuit are provided. In one aspect, the embodiment of the present disclosure uses the digital calibration method to calibrate compensation of a circuit to be calibrated, output of the circuit to be calibrated is sampled and tested multiple times, and whether a current test compensation calibration code value can make the circuit to be calibrated meet specified accuracy is judged based on a probability that the output result is a target result. Through sampling the output of the circuit to be calibrated multiple times, the selected compensation calibration code has higher accuracy.

A random bit circuit includes four storage cells controlled by four different word lines. The first storage cell and the second storage cell are disposed along a first direction sequentially, and the first storage cell and the third storage cell are disposed along a second direction sequentially. The third storage cell and the fourth storage cell are disposed along the first direction sequentially. The first storage cell and the fourth storage cell are coupled in series, and the second storage cell and the third storage cell are coupled in series.

A random bit circuit includes four storage cells controlled by four different word lines. The first storage cell and the second storage cell are disposed along a first direction sequentially, and the first storage cell and the third storage cell are disposed along a second direction sequentially. The third storage cell and the fourth storage cell are disposed along the first direction sequentially. The first storage cell and the fourth storage cell are coupled in series, and the second storage cell and the third storage cell are coupled in series.

A read-only memory cell array includes a first storage state memory cell and a second storage state memory cell. The first storage state memory cell includes a first transistor and a second transistor. The first transistor is connected to a source line and a word line. The second transistor is connected to the first transistor and a first bit line. The second storage state memory cell includes a third transistor and a fourth transistor. The third transistor is connected to the source line and the word line. The fourth transistor is connected to the third transistor and a second bit line. A gate terminal of the fourth transistor is connected to a gate terminal of the third transistor.

Embodiments provide a true random number generator. The true random number generator may include a first ring oscillator having a first frequency, a second ring oscillator having a second frequency, a third ring oscillator having a third frequency, and a capacitor connected between the second ring oscillator and the third ring oscillator to provide a capacitive coupling therebetween. The second frequency is lower than the first frequency, and the third frequency is lower than the second frequency. The true random number generator may further include a D-type flip-flop having a data input connected to an output of the first ring oscillator and having a clock input connected to an output of the third ring oscillator, wherein the D-type flip-flop is configured to generate an output signal representing a sequence of random numbers.

A true random number generator based on a voltage-controlled oscillator includes a thermal noise generator, a ring oscillator, a voltage-controlled oscillator, a D flip-flop, and a post-processing circuit. The D flip-flop has a clock terminal, an input terminal, and an output terminal. An output terminal of the thermal noise generator is connected with an input terminal of the voltage-controlled oscillator. An output terminal of the voltage-controlled oscillator is connected with the clock terminal of the D flip-flop. An output terminal of the ring oscillator is connected with the input terminal of the D flip-flop. The output terminal of the D flip-flop is connected with an input terminal of the post-processing circuit. An input terminal of the thermal noise generator is connected with a reference level. The thermal noise generator includes a digital-analog converter, an operational amplifier, a first resistor, a second resistor, a third resistor, and a fourth resistor.

A true random number generator based on a voltage-controlled oscillator includes a thermal noise generator, a ring oscillator, a voltage-controlled oscillator, a D flip-flop, and a post-processing circuit. The D flip-flop has a clock terminal, an input terminal, and an output terminal. An output terminal of the thermal noise generator is connected with an input terminal of the voltage-controlled oscillator. An output terminal of the voltage-controlled oscillator is connected with the clock terminal of the D flip-flop. An output terminal of the ring oscillator is connected with the input terminal of the D flip-flop. The output terminal of the D flip-flop is connected with an input terminal of the post-processing circuit. An input terminal of the thermal noise generator is connected with a reference level. The thermal noise generator includes a digital-analog converter, an operational amplifier, a first resistor, a second resistor, a third resistor, and a fourth resistor.