A novel and useful system and method of accelerated learning in neural networks using silicon based quantum dot arrays. Unitary noise is derived from a probability of detecting a particle within a quantum dot array structure comprising position based charge qubits with two time independent basis states |0> and |1>. A two level electron tunneling device such as an interface device, qubit or other quantum structure is used to generate quantum noise. The electron tunneling device includes a reservoir of particles, a quantum dot, and a barrier that is used to control tunneling between the reservoir and the quantum dot. Controlling the bias applied to the barrier controls the probability of detection. Thus, the probability density function (PDF) of the output unitary noise can be controlled to correspond to a desired probability. The quantum unitary noise is injected into one or more layers of an artificial neural network (ANN) to improve the learning and training process. The quantum noise source is also used to perform stochastic rounding in the ANN. The PDF of the quantum noise source output is set to a desired value in accordance with the remainder portion of input numbers within the layers of the ANN to be rounded.

A novel and useful system and method of accelerated learning in neural networks using silicon based quantum dot arrays. Unitary noise is derived from a probability of detecting a particle within a quantum dot array structure comprising position based charge qubits with two time independent basis states |0> and |1>. A two level electron tunneling device such as an interface device, qubit or other quantum structure is used to generate quantum noise. The electron tunneling device includes a reservoir of particles, a quantum dot, and a barrier that is used to control tunneling between the reservoir and the quantum dot. Controlling the bias applied to the barrier controls the probability of detection. Thus, the probability density function (PDF) of the output unitary noise can be controlled to correspond to a desired probability. The quantum unitary noise is injected into one or more layers of an artificial neural network (ANN) to improve the learning and training process. The quantum noise source is also used to perform stochastic rounding in the ANN. The PDF of the quantum noise source output is set to a desired value in accordance with the remainder portion of input numbers within the layers of the ANN to be rounded.

Example devices are described that include a computational unit configured to process first set of data bits encoding a first numerical value and a second set of data bits encoding a second numerical value. The computational unit includes a bit-stream generator configured to generate bit combinations representing first and second bit sequences that encode the first and second numerical values, respectively, based on a proportion of the data bits in the sequence that are high relative to the total data bits. The first bit sequence is generated using a first Sobol sequence source, and the second bit sequence is generated using a second Sobol sequence source different from the first Sobol sequence source. The device also includes computation logic configured to perform a computational operation on the bit combinations and produce an output bit-stream having a set of data bits indicating a result of the computational operation.

Example devices are described that include a computational unit configured to process first set of data bits encoding a first numerical value and a second set of data bits encoding a second numerical value. The computational unit includes a bit-stream generator configured to generate bit combinations representing first and second bit sequences that encode the first and second numerical values, respectively, based on a proportion of the data bits in the sequence that are high relative to the total data bits. The first bit sequence is generated using a first Sobol sequence source, and the second bit sequence is generated using a second Sobol sequence source different from the first Sobol sequence source. The device also includes computation logic configured to perform a computational operation on the bit combinations and produce an output bit-stream having a set of data bits indicating a result of the computational operation.

An electromagnetic interference reducing circuit is provided. A first random number generator generates a plurality of first random number signals each having a plurality of triangular waves. Each of the triangular waves has a plurality of steps. The first random number generator generates a plurality of first random numbers and modulates each of the first random number signals according to the first random numbers. The first random number generator repeatedly counts, repeatedly removes, or does not count time of the steps of each of the triangular waves of each of the first random number signals according to one of the first random numbers. A first oscillator generates a first oscillating signal. A motor controller circuit controls a plurality of switch components of a motor respectively according to the first random number signals based on the first oscillating signal.

An electromagnetic interference reducing circuit is provided. A first random number generator generates a plurality of first random number signals each having a plurality of triangular waves. Each of the triangular waves has a plurality of steps. The first random number generator generates a plurality of first random numbers and modulates each of the first random number signals according to the first random numbers. The first random number generator repeatedly counts, repeatedly removes, or does not count time of the steps of each of the triangular waves of each of the first random number signals according to one of the first random numbers. A first oscillator generates a first oscillating signal. A motor controller circuit controls a plurality of switch components of a motor respectively according to the first random number signals based on the first oscillating signal.

A propagation delay balance circuit includes a signal generating circuit, a path switching element, and a signal change detecting element. The signal generating circuit includes delay chains for outputting delay signals respectively. The path switching element has input terminals and output terminals. Each output terminal of the path switching element is electrically connected to the input terminal of each delay chain one-to-one, and input terminals of the path switching element are electrically connected one-to-one to the output terminals of the delay chains. The path switching element is controlled by the path switching controlling signal to change the one-to-one internal electrical connection between input terminals and output terminals of the path switching element. The signal change detecting element is electrically connected to the path switching element, and generates a path switching controlling signal according to delay signals of the path switching element.

A propagation delay balance circuit includes a signal generating circuit, a path switching element, and a signal change detecting element. The signal generating circuit includes delay chains for outputting delay signals respectively. The path switching element has input terminals and output terminals. Each output terminal of the path switching element is electrically connected to the input terminal of each delay chain one-to-one, and input terminals of the path switching element are electrically connected one-to-one to the output terminals of the delay chains. The path switching element is controlled by the path switching controlling signal to change the one-to-one internal electrical connection between input terminals and output terminals of the path switching element. The signal change detecting element is electrically connected to the path switching element, and generates a path switching controlling signal according to delay signals of the path switching element.

A memory controller for controlling an operation of a semiconductor memory device including a memory block including a plurality of sub-blocks. The memory controller includes a randomizer. The randomizer includes: seed table storage configured to store a plurality of seed tables respectively corresponding to the plurality of sub-blocks, and to generate a seed, based on sub-block information of received original data; a random sequence generator configured to generate a random sequence, based on the seed generated by the seed table storage; and an operating component configured to generate random data, based on the random sequence and the original data.

A memory controller for controlling an operation of a semiconductor memory device including a memory block including a plurality of sub-blocks. The memory controller includes a randomizer. The randomizer includes: seed table storage configured to store a plurality of seed tables respectively corresponding to the plurality of sub-blocks, and to generate a seed, based on sub-block information of received original data; a random sequence generator configured to generate a random sequence, based on the seed generated by the seed table storage; and an operating component configured to generate random data, based on the random sequence and the original data.