An N-bit linear feedback shift register includes P parallel chains of flip flops each having an input and output. The input is coupled to output of an XOR circuit for that parallel chain. Inputs of the XOR circuit for that parallel chain are coupled to outputs of different flip flops of the P parallel chains according to exponents of a primitive polynomial of order N−1. The flip flops of the P parallel chains of flip flops are clocked by a second clock. At each rising edge of the second clock, P LFSR pre-outputs are respectively produced from the outputs of last flip flops of each of P parallel chains of flip flops. Readout circuitry clocked by a first clock having a frequency that is P times that of the first clock passes a different one of the P pre-LFSR outputs at each clock cycle as a LFSR output.

At least some aspects of the present disclosure provide for a system. In some examples, the system includes a pulse width modulation (PWM) generator configured to generate a PWM signal. The PWM generator generates the PWM signal by generating a first signal having a first dithering profile and a first frequency bandwidth, generating a second signal having a second dithering profile and a second frequency bandwidth greater than the first frequency bandwidth, modulating the second signal with the first signal to generate a dual random spread spectrum signal, and generating the pulse width modulation signal according to the dual random spread spectrum signal.

The present description concerns a method of generation of a sequence of pseudo-random digital codes enabling to perform a permutation (3) of a first set of values (V) into a second set of values (Vp) based on said digital codes (CPos) representative of positions (j) of values (Vi) of the first set in the second set, including the steps of: generating, by successive iterations, a chain of numbers, called seed numbers, from an initial pseudo-random seed number (W0) by application of a first function (24, 26) from a seed number to the next seed number; applying a second function to each seed number of the chain to obtain each position code (CPos(j)), the second function including at least one permutation (PERM) followed by a bijection (BIJ).

The present description concerns a method of generation of a sequence of pseudo-random digital codes enabling to perform a permutation (3) of a first set of values (V) into a second set of values (Vp) based on said digital codes (CPos) representative of positions (j) of values (Vi) of the first set in the second set, including the steps of: generating, by successive iterations, a chain of numbers, called seed numbers, from an initial pseudo-random seed number (W0) by application of a first function (24, 26) from a seed number to the next seed number; applying a second function to each seed number of the chain to obtain each position code (CPos(j)), the second function including at least one permutation (PERM) followed by a bijection (BIJ).

A multi-frequency uniformization carrier wave slope random distribution pulse width modulation method, includes: (1) selecting a required random carrier wave sequence and a modulating wave, and after the two are compared, generating a switch device drive signal for pulse width modulation; (2) determining a multiple n of an equivalent carrier frequency f of the random carrier wave sequence, and selecting a main circuit topology; and (3) inputting the switch device drive signal generated in (1) into the main circuit topology of (2) to perform multi-frequency uniformization carrier wave slope random distribution pulse width modulation. The disclosure can improve a frequency domain distribution bandwidth of a harmonic wave without changing the mean and variance of a random carrier wave sequence, and realizes uniform distribution of carrier waves and multiple harmonic peaks near a doubled frequency of the carrier waves in a wider frequency domain.

A multi-frequency uniformization carrier wave slope random distribution pulse width modulation method, includes: (1) selecting a required random carrier wave sequence and a modulating wave, and after the two are compared, generating a switch device drive signal for pulse width modulation; (2) determining a multiple n of an equivalent carrier frequency f of the random carrier wave sequence, and selecting a main circuit topology; and (3) inputting the switch device drive signal generated in (1) into the main circuit topology of (2) to perform multi-frequency uniformization carrier wave slope random distribution pulse width modulation. The disclosure can improve a frequency domain distribution bandwidth of a harmonic wave without changing the mean and variance of a random carrier wave sequence, and realizes uniform distribution of carrier waves and multiple harmonic peaks near a doubled frequency of the carrier waves in a wider frequency domain.

Technologies are provided for generation of programmable pulse signals using inverse chaotic maps, without reliance on a clocking signal. Some embodiments of the technologies include an apparatus that can receive a sequence of bits having a defined number of bits, where the sequence of bits represent a desired continuous pulse signal having a programmable width in time-domain. The apparatus can also can receive a precursor continuous pulse signal having an arbitrary width in time-domain that fits within the dynamic range of the apparatus. The apparatus can generate the desired continuous pulse signal by transforming the precursor continuous pulse signal using the sequence of bits and an inverse chaotic map.

A system for providing security in a computer system is provided. The system includes a plurality of ring oscillators and one or more logic circuits. The ring oscillators are equipped with a respective plurality of counters to count impulses of oscillating outputs of the ring oscillators. The one or more logic circuits start and stop the respective plurality of counters over repeated counting periods, and select a group of ring oscillators from the plurality of ring oscillators. The one or more logic circuits also determine a correlation between oscillating outputs of the group of ring oscillators. The one or more logic circuits further generate a notification indicating interference in the group of ring oscillators and thereby the plurality of ring oscillators when the correlation is above a predefined threshold correlation.

A memory device that includes a memory array and a memory controller is introduced. The memory controller is configured to adjust a program strength of the program pulse according to the configurable ratio of the first bit value and the second bit value to generate an adjusted program pulse or to adjust a bias voltage pair according to the configurable ratio of the first bit value and the second bit value to generate an adjusted bias voltage pair. The memory controller is further configured to generate the random bit stream with the configurable ratio of the first bit value and the second bit value according to the data stored in the plurality of memory cells included in the memory array after applying the adjusted program pulse or according to the data stored in the plurality of memory cells after being biased by the adjusted bias voltage pair.

A memory device that includes a memory array and a memory controller is introduced. The memory controller is configured to adjust a program strength of the program pulse according to the configurable ratio of the first bit value and the second bit value to generate an adjusted program pulse or to adjust a bias voltage pair according to the configurable ratio of the first bit value and the second bit value to generate an adjusted bias voltage pair. The memory controller is further configured to generate the random bit stream with the configurable ratio of the first bit value and the second bit value according to the data stored in the plurality of memory cells included in the memory array after applying the adjusted program pulse or according to the data stored in the plurality of memory cells after being biased by the adjusted bias voltage pair.