A fluctuating oscillator includes: an adder that has an input terminal to which an input signal including a main signal and an uncorrelated signal that is uncorrelated with the main signal and is higher in frequency than the main signal is input, and adds a feedback signal to the input signal; a threshold discrimination unit that generates a pulse signal by comparing an addition signal added by the adder with a threshold; a transient response unit that generates an output signal by transiently responding the generated pulse signal; and a feedback loop that feeds back the output signal to the adder as the feedback signal.

A fluctuating oscillator includes: an adder that has an input terminal to which an input signal including a main signal and an uncorrelated signal that is uncorrelated with the main signal and is higher in frequency than the main signal is input, and adds a feedback signal to the input signal; a threshold discrimination unit that generates a pulse signal by comparing an addition signal added by the adder with a threshold; a transient response unit that generates an output signal by transiently responding the generated pulse signal; and a feedback loop that feeds back the output signal to the adder as the feedback signal.

An oscillator circuit includes a plurality of inverters connected in a cascade, at least first and second feedback taps, and alternation circuitry. The at least first and second feedback taps are configured to feed-back at least respective first and second output signals taken from at least respective first and second points in the cascade. The alternation circuitry is configured to derive an input signal from at least the first and second output signals by alternating between at least the first and second feedback taps, and to apply the input signal to an input of the cascade.

An oscillator circuit includes a plurality of inverters connected in a cascade, at least first and second feedback taps, and alternation circuitry. The at least first and second feedback taps are configured to feed-back at least respective first and second output signals taken from at least respective first and second points in the cascade. The alternation circuitry is configured to derive an input signal from at least the first and second output signals by alternating between at least the first and second feedback taps, and to apply the input signal to an input of the cascade.

A random number generator that includes control circuit, an oscillation circuit, an oscillation detection circuit and a latch circuit is introduced. The control circuit sweeps a configuration of a bias control signal among a plurality of configurations. The oscillation circuit generates an oscillation signal based on the configuration of the bias control signal. The oscillation detection circuit detects an onset of the oscillation signal, and outputs a lock signal. The latch circuit latches the oscillation signal according to a trigger signal to output a random number, wherein the trigger signal is asserted after the lock signal is outputted, and the configuration of bias control signal is locked after the lock signal is outputted. A method for generating a random number and an operation method of a random number generator are also introduced.

A random number generator that includes control circuit, an oscillation circuit, an oscillation detection circuit and a latch circuit is introduced. The control circuit sweeps a configuration of a bias control signal among a plurality of configurations. The oscillation circuit generates an oscillation signal based on the configuration of the bias control signal. The oscillation detection circuit detects an onset of the oscillation signal, and outputs a lock signal. The latch circuit latches the oscillation signal according to a trigger signal to output a random number, wherein the trigger signal is asserted after the lock signal is outputted, and the configuration of bias control signal is locked after the lock signal is outputted. A method for generating a random number and an operation method of a random number generator are also introduced.

Aggressor rows may be detected by comparing access count values of word lines to a threshold value. Based on the comparison, a word line may be determined to be an aggressor row. The threshold value may be dynamically generated, such as a random number generated by a random number generator. In some examples, a random number may be generated each time an activation command is received. Responsive to detecting an aggressor row, a targeted refresh operation may be performed.

An apparatus includes a carry chain circuit and a detector circuit. The carry chain circuit includes a plurality of stages. Each stage of the plurality of stages includes a plurality of lookup table elements coupled in sequence. The carry chain circuit propagates a clock signal through the plurality of lookup table elements of the plurality of stages. The detector circuit determines, based on a value of the clock signal stored by a final lookup table element of each stage of the plurality of stages, which stage of the plurality stages contains an edge of the clock signal. The detector circuit then outputs a zero if the determined stage is assigned to a first group of the plurality of stages and a one if the determined stage is assigned to a second group of the plurality of stages.

An apparatus includes a carry chain circuit and a detector circuit. The carry chain circuit includes a plurality of stages. Each stage of the plurality of stages includes a plurality of lookup table elements coupled in sequence. The carry chain circuit propagates a clock signal through the plurality of lookup table elements of the plurality of stages. The detector circuit determines, based on a value of the clock signal stored by a final lookup table element of each stage of the plurality of stages, which stage of the plurality stages contains an edge of the clock signal. The detector circuit then outputs a zero if the determined stage is assigned to a first group of the plurality of stages and a one if the determined stage is assigned to a second group of the plurality of stages.

An oscillation unit (101), a measurement unit (102), and a bit generation unit (103) are included. The measurement unit (102) chronologically measures oscillation (for example, thermal oscillation) of a set frequency generated in the oscillation unit (101) at each set time. The bit generation unit (103) generates a bit string by allocating one bit of 0 or 1 to each of sine and cosine components of the oscillation measured by the measurement unit (102).