An image sensor may include an array of image sensor pixels. Pixel control circuitry may provide control signals to the array of image sensor pixels. The pixel control circuitry may include a plurality of driver units that each generate a control signal for a different set of image sensor pixels. The control signal generated by each of the driver units may be delayed relative to each other. A voltage-controlled delay line may provide delayed outputs to each of the driver units. Delay lock circuitry coupled to the voltage-controlled delay line may fix the delay exhibited across the delay line using corresponding global and local bias voltages provided to each of the inverters in the delay line.

A system comprises a positive voltage supply node and a negative voltage supply node configured for connection to a load, a power source coupled between the positive voltage supply node and the negative voltage supply node, an energy storage device, a solid-state switch, and a control system. The energy storage device and the solid-state switch are connected in series between the positive voltage supply node and the negative voltage supply node. The control system is configured to control activation and deactivation of the solid-state switch to (i) allow the energy storage device to be discharged and supply power to a load, and to (ii) modulate an amount of charging current that flows through the energy storage device from the power source (or load) to recharge the energy storage device.

A system comprises a positive voltage supply node and a negative voltage supply node configured for connection to a load, a power source coupled between the positive voltage supply node and the negative voltage supply node, an energy storage device, a solid-state switch, and a control system. The energy storage device and the solid-state switch are connected in series between the positive voltage supply node and the negative voltage supply node. The control system is configured to control activation and deactivation of the solid-state switch to (i) allow the energy storage device to be discharged and supply power to a load, and to (ii) modulate an amount of charging current that flows through the energy storage device from the power source (or load) to recharge the energy storage device.

Provided are a delay-locked loop (DLL), a delay locking method, a clock synchronization circuit, and a memory. The DLL includes: a frequency division module, configured to receive an input clock signal, perform frequency division on the input clock signal, and output an intermediate clock signal; a first adjustable delay line, configured to receive the intermediate clock signal, adjust and transmit the intermediate clock signal, and output a synchronous clock signal; a delay module, configured to receive the input clock signal, perform delay transmission on the input clock signal, and output a sampling clock signal; and a latching module, configured to receive the sampling clock signal and the synchronous clock signal, latch the synchronous clock signal on the basis of the sampling clock signal, and output a group of target clock signals.

Provided are a delay-locked loop (DLL), a delay locking method, a clock synchronization circuit, and a memory. The DLL includes: a frequency division module, configured to receive an input clock signal, perform frequency division on the input clock signal, and output an intermediate clock signal; a first adjustable delay line, configured to receive the intermediate clock signal, adjust and transmit the intermediate clock signal, and output a synchronous clock signal; a delay module, configured to receive the input clock signal, perform delay transmission on the input clock signal, and output a sampling clock signal; and a latching module, configured to receive the sampling clock signal and the synchronous clock signal, latch the synchronous clock signal on the basis of the sampling clock signal, and output a group of target clock signals.

A semiconductor device includes a first dummy group having a first set of dummy transistors; a first delay cell having a first set of active transistors; a second delay cell having a second set of active transistors; a second dummy group having a second set of dummy transistors; and relative to a first direction the first and second dummy groups and the first and second delay cells being arranged in a first sequence arranged as the first dummy group, the first delay cell, the second delay cell, and the second dummy group; and the first and second delay cells being free from having another dummy group therebetween.

A semiconductor device includes a first dummy group having a first set of dummy transistors; a first delay cell having a first set of active transistors; a second delay cell having a second set of active transistors; a second dummy group having a second set of dummy transistors; and relative to a first direction the first and second dummy groups and the first and second delay cells being arranged in a first sequence arranged as the first dummy group, the first delay cell, the second delay cell, and the second dummy group; and the first and second delay cells being free from having another dummy group therebetween.

A semiconductor device includes a first dummy group having a first set of dummy transistors; a first delay cell having a first set of active transistors; a second delay cell having a second set of active transistors; a second dummy group having a second set of dummy transistors; and relative to a first direction the first and second dummy groups and the first and second delay cells being arranged in a first sequence arranged as the first dummy group, the first delay cell, the second delay cell, and the second dummy group; and the first and second delay cells being free from having another dummy group therebetween.

A semiconductor device includes a first dummy group having a first set of dummy transistors; a first delay cell having a first set of active transistors; a second delay cell having a second set of active transistors; a second dummy group having a second set of dummy transistors; and relative to a first direction the first and second dummy groups and the first and second delay cells being arranged in a first sequence arranged as the first dummy group, the first delay cell, the second delay cell, and the second dummy group; and the first and second delay cells being free from having another dummy group therebetween.

An image sensor may include an array of image sensor pixels. Pixel control circuitry may provide control signals to the array of image sensor pixels. The pixel control circuitry may include a plurality of driver units that each generate a control signal for a different set of image sensor pixels. The control signal generated by each of the driver units may be delayed relative to each other. A voltage-controlled delay line may provide delayed outputs to each of the driver units. Delay lock circuitry coupled to the voltage-controlled delay line may fix the delay exhibited across the delay line using corresponding global and local bias voltages provided to each of the inverters in the delay line.