A method and apparatus for generating a frequency comb. A sine wave comprising samples is generated at a selected sampling rate and a selected increment corresponding to a number of samples for a period of the sine wave using a lookup table or a CORDIC algorithm. The sine wave is processed by a universal differential equation to generate the frequency comb. Characteristics of the frequency comb generated from the sine wave are controlled by changing the sampling rate and the increment.

A method and apparatus for generating a frequency comb. A sine wave comprising samples is generated at a selected sampling rate and a selected increment corresponding to a number of samples for a period of the sine wave using a lookup table or a CORDIC algorithm. The sine wave is processed by a universal differential equation to generate the frequency comb. Characteristics of the frequency comb generated from the sine wave are controlled by changing the sampling rate and the increment.

A method and apparatus for generating a frequency comb. A sine wave comprising samples is generated at a selected sampling rate and a selected increment corresponding to a number of samples for a period of the sine wave using a lookup table or a CORDIC algorithm. The sine wave is processed by a universal differential equation to generate the frequency comb. Characteristics of the frequency comb generated from the sine wave are controlled by changing the sampling rate and the increment.

A method and apparatus for generating a frequency comb. A sine wave comprising samples is generated at a selected sampling rate and a selected increment corresponding to a number of samples for a period of the sine wave using a lookup table or a CORDIC algorithm. The sine wave is processed by a universal differential equation to generate the frequency comb. Characteristics of the frequency comb generated from the sine wave are controlled by changing the sampling rate and the increment.

A method for synchronized injection of impedance into high voltage (HV) transmission line is disclosed. The method includes generating, by a plurality of impedance injection units (IIUs) coupled to the HV transmission line, impedance injection waves that cumulatively form a pseudo-sinusoidal wave. The method further includes optimizing, by the plurality of IIUs, the pseudo-sinusoidal wave to represent a pure sinusoidal wave. The method further includes injecting, by the plurality of IIUs, the pseudo-sinusoidal wave, as impedance, into the HV transmission line. The plurality of IIUs form multiple connection configurations in sequence, each connection configuration comprising one IIU or multiple IIUs in series, parallel or combination thereof, coupled to the HV transmission line.

A signal generator includes a processing unit. The signal generator is configured to generate at least one periodic output signal. The output signal comprises a triangular-waveform signal. A frequency and an amplitude of the output signal are adjustable. The signal generator is configured to receive an input parameter. The input parameter comprises at least one piece of information about a setpoint amplitude and a setpoint frequency of the output signal. The processing unit is configured to determine a signal direction of the output signal. The processing unit is configured to determine a step size. The processing unit is configured to apply the step size to an actual amplitude based on the signal direction for a number of clock cycles. The number of clock cycles is dependent on the setpoint frequency of the output signal.

A signal generator includes a processing unit. The signal generator is configured to generate at least one periodic output signal. The output signal comprises a triangular-waveform signal. A frequency and an amplitude of the output signal are adjustable. The signal generator is configured to receive an input parameter. The input parameter comprises at least one piece of information about a setpoint amplitude and a setpoint frequency of the output signal. The processing unit is configured to determine a signal direction of the output signal. The processing unit is configured to determine a step size. The processing unit is configured to apply the step size to an actual amplitude based on the signal direction for a number of clock cycles. The number of clock cycles is dependent on the setpoint frequency of the output signal.

A method for initializing a phase adder circuit including a multiplier circuit with its two inputs receiving signals of frequency f.sub.o, a mixer circuit, an amplifier circuit, a low pass loop filter, and a voltage controlled oscillator (VCO), the method including: during a first phase, determining a reference voltage which when applied to the VCO causes it to produce a signal having a frequency of nf.sub.0; during a second phase, supplying a signal of frequency nf.sub.o to a first input of the mixer and a signal of frequency (nf.sub.o+Δf) to a second input of the mixer; and determining an adjustment signal which when applied to the amplifier circuit causes the amplifier circuit to output a signal having a DC component equal to the reference voltage; and during a third phase, forming a primary phase locked loop (PLL) circuit including the mixer, the amplifier circuit, the low pass loop filter and the VCO; and applying the adjustment signal to the amplifier circuit.

A method for initializing a phase adder circuit including a multiplier circuit with its two inputs receiving signals of frequency f.sub.o, a mixer circuit, an amplifier circuit, a low pass loop filter, and a voltage controlled oscillator (VCO), the method including: during a first phase, determining a reference voltage which when applied to the VCO causes it to produce a signal having a frequency of nf.sub.0; during a second phase, supplying a signal of frequency nf.sub.o to a first input of the mixer and a signal of frequency (nf.sub.o+Δf) to a second input of the mixer; and determining an adjustment signal which when applied to the amplifier circuit causes the amplifier circuit to output a signal having a DC component equal to the reference voltage; and during a third phase, forming a primary phase locked loop (PLL) circuit including the mixer, the amplifier circuit, the low pass loop filter and the VCO; and applying the adjustment signal to the amplifier circuit.

A method of recovering information encoded by a modulated sinusoidal waveform having first, second, third and fourth data notches at respective phase angles, where a power of the modulated sinusoidal waveform is reduced relative to a power of an unmodulated sinusoidal waveform within selected ones of the first, second, third and fourth data notches so as to encode input digital data. The method includes receiving the modulated sinusoidal waveform and generating digital values representing the modulated sinusoidal waveform. A digital representation of the unmodulated sinusoidal waveform is subtracted from the digital values in order to generate a received digital data sequence, which includes digital data notch values representative of the amplitude of the modulated sinusoidal waveform within the first, second, third and fourth data notches. The input digital data is then estimated based upon the digital data notch values.