A system and method for generating a radio frequency (RF) waveform are described. The method includes defining a train of on-off pulses separated by an off state having no on-off pulses. The method further includes applying a multi-level pulse waveform that adjusts a magnitude of each of the on-off pulses to generate an RF waveform. The method includes sending the RF waveform to an electrode.

A system and method for generating a radio frequency (RF) waveform are described. The method includes defining a train of on-off pulses separated by an off state having no on-off pulses. The method further includes applying a multi-level pulse waveform that adjusts a magnitude of each of the on-off pulses to generate an RF waveform. The method includes sending the RF waveform to an electrode.

A method of recovering information encoded by a modulated sinusoidal waveform having first, second, third and fourth data notches at respective phase angles, where a power of the modulated sinusoidal waveform is reduced relative to a power of an unmodulated sinusoidal waveform within selected ones of the first, second, third and fourth data notches so as to encode input digital data. The method includes receiving the modulated sinusoidal waveform and generating digital values representing the modulated sinusoidal waveform. A digital representation of the unmodulated sinusoidal waveform is subtracted from the digital values in order to generate a received digital data sequence, which includes digital data notch values representative of the amplitude of the modulated sinusoidal waveform within the first, second, third and fourth data notches. The input digital data is then estimated based upon the digital data notch values.

A system and method for waveform modulation includes encoding input digital data at selected phase angles of an unmodulated sinusoidal waveform. The encoding includes selectively reducing a power of the unmodulated sinusoidal waveform at the selected phase angles in accordance with bit values of the input digital data so as to respectively define first, second, third and fourth data notches in the modulated sinusoidal waveform. An encoded analog waveform is then generated from a digital representation of the modulated sinusoidal waveform. The encoding is performed so that energies associated with the first and third data notches are balanced and energies associated with second and fourth data notches are also balanced. Each of the energies corresponds to a cumulative power difference between a power of the unmodulated sinusoidal waveform and a power of the modulated sinusoidal waveform over a phase angle range subtended by one of the data notches.

A system and method for narrowband sinewave modulation. The system includes an input buffer for storing input digital data and a sub-periodic modulator for encoding the input digital data in a periodic waveform. The sub-periodic modulator encodes one or more bit values of the input digital data within each period of the periodic waveform. One or more digital-to-analog converters generate an encoded analog waveform from a digital representation of the periodic waveform wherein the encoded analog waveform is of a frequency f and a power P. The encoding is performed by the sub-periodic modulator such that any signal of frequency f resulting from the encoding is of a power P at least 50 dB less than power P, where f is offset from f by more than 25 Hz.

A method for initializing a phase adder circuit including a multiplier circuit with its two inputs receiving signals of frequency f.sub.o, a mixer circuit, an amplifier circuit, a low pass loop filter, and a voltage controlled oscillator (VCO), the method including: during a first phase, determining a reference voltage which when applied to the VCO causes it to produce a signal having a frequency of nf.sub.0; during a second phase, supplying a signal of frequency nf.sub.o to a first input of the mixer and a signal of frequency (nf.sub.o+f) to a second input of the mixer; and determining an adjustment signal which when applied to the amplifier circuit causes the amplifier circuit to output a signal having a DC component equal to the reference voltage; and during a third phase, forming a primary phase locked loop (PLL) circuit including the mixer, the amplifier circuit, the low pass loop filter and the VCO; and applying the adjustment signal to the amplifier circuit.

A method for initializing a phase adder circuit including a multiplier circuit with its two inputs receiving signals of frequency f.sub.o, a mixer circuit, an amplifier circuit, a low pass loop filter, and a voltage controlled oscillator (VCO), the method including: during a first phase, determining a reference voltage which when applied to the VCO causes it to produce a signal having a frequency of nf.sub.0; during a second phase, supplying a signal of frequency nf.sub.o to a first input of the mixer and a signal of frequency (nf.sub.o+f) to a second input of the mixer; and determining an adjustment signal which when applied to the amplifier circuit causes the amplifier circuit to output a signal having a DC component equal to the reference voltage; and during a third phase, forming a primary phase locked loop (PLL) circuit including the mixer, the amplifier circuit, the low pass loop filter and the VCO; and applying the adjustment signal to the amplifier circuit.

In some examples, a device includes a gate driver circuit and a control circuit configured to generate a first signal and a second signal, a duty cycle of the first signal encoding an amplitude of an electrical current having a sinusoidal shape, and a duty cycle of the second signal encoding a phase angle of the electrical current. The control circuit is configured to deliver the first and second signals to the gate driver circuit, which is configured to determine a duty cycle of a driver signal as a function of the first signal and of the second signal. The gate driver circuit is also configured to deliver the driver signal to a switch to cause the electrical current having the sinusoidal shape to be delivered to an electrical load.

In some examples, a device includes a gate driver circuit and a control circuit configured to generate a first signal and a second signal, a duty cycle of the first signal encoding an amplitude of an electrical current having a sinusoidal shape, and a duty cycle of the second signal encoding a phase angle of the electrical current. The control circuit is configured to deliver the first and second signals to the gate driver circuit, which is configured to determine a duty cycle of a driver signal as a function of the first signal and of the second signal. The gate driver circuit is also configured to deliver the driver signal to a switch to cause the electrical current having the sinusoidal shape to be delivered to an electrical load.

A data communications system and method having high spectral efficiency. The method includes encoding input digital data using a plurality of symbol waveforms. Each symbol waveform occupies a period of a composite encoded waveform and represents one or more bits of the input digital data. Each symbol waveform has a first elliptical segment and a second elliptical segment of opposite polarity. The encoding includes defining each symbol waveform so that (i) a zero crossing from the first elliptical segment to the second elliptical segment of the symbol waveform is different for each of the symbol waveforms, and (ii) an energy of the first elliptical segment of the symbol waveform is substantially equal to an energy of the second elliptical segment of the symbol waveform. An encoded analog waveform is generated, using a digital-to-analog converter, from a digital representation of the composite encoded waveform.