Embodiments disclosed herein generally relate to electronic devices, and more specifically, to a waveform generation circuit for input devices. One or more embodiments provide a new waveform generator for an integrated touch and display driver (TDDI) and methods for generating a waveform for capacitive sensing with a finely tunable sensing frequency. A waveform generator includes accumulator circuitry, truncation circuitry, and saturation circuitry. The accumulator circuitry is configured to accumulate the phase increment value based on a clock signal, and output the accumulated phase increment value. The truncation circuitry configured to drop one or more bits of the accumulated phase increment value to output a truncated value. The saturation circuitry is configured to compare the truncated value to a saturation limit and output a signal corresponding to accessed data samples.

The present invention relates to a technology capable of compensating for a frequency error in a quadrature relaxation oscillator. The quadrature relaxation oscillator generates a signal at a desired frequency by using a resistor and a capacitor which are less sensitive to a PVT (Process, Voltage, Temperature) variation, generates a signal at a desired frequency by compensating for an error from design, which is caused by a mismatch between circuits due to a characteristic of a semiconductor process, through a feedback lop, and removes noise.

Neuromuscular stimulation is widely used for rehabilitation and movement assist devices, due to its safety, efficacy, and ease of operation. For repeatable and accurate muscular contractions, a voltage controlled current sources (VCCS) with high compliance is required. Conventional VCCS design requires high-voltage rated operational amplifiers, which are expensive and consume large power. Moreover, conventional stimulators are not viable for simultaneous stimulation of muscle synergies, as they require multiple VCCS operating at the same time. This invention presents a neuromuscular stimulator with a multistage driver circuit wherein, a VCCS connected to an output driving stage comprising of folded-cascode transistor buffers and a bidirectional current mirror circuit. The multistage driver circuit uses inexpensive low-voltage rated operational amplifiers that consume 95% less power. Additionally, we disclose a stimulation method wherein only a single current source drives several output drivers connected in series or parallel to simultaneously stimulate multiple muscles or muscle synergies.

A circuit, comprising a trapezoidal generator that comprises digital logic configured to couple at a first input to a loop controller and at a second input to a buck-boost region detector and a driver coupled to an output of the digital logic and configured to couple to at least one power transistor of a power converter.

A circuit, comprising a trapezoidal generator that comprises digital logic configured to couple at a first input to a loop controller and at a second input to a buck-boost region detector and a driver coupled to an output of the digital logic and configured to couple to at least one power transistor of a power converter.

A drive waveform setting unit sets a drive waveform of a drive signal, and a drive current is applied to a drive coil provided in a response force generation mechanism in accordance with the drive waveform. The drive waveform has a first drive section in which a signal intensity increases linearly and a second drive section including a peak. An increase rate of the signal intensity in the second drive section is lower than that in the first drive section. As a result, it is easy to follow the frequency characteristics of a driver circuit, and it is possible to increase a voltage to be applied to a drive coil.

A drive waveform setting unit sets a drive waveform of a drive signal, and a drive current is applied to a drive coil provided in a response force generation mechanism in accordance with the drive waveform. The drive waveform has a first drive section in which a signal intensity increases linearly and a second drive section including a peak. An increase rate of the signal intensity in the second drive section is lower than that in the first drive section. As a result, it is easy to follow the frequency characteristics of a driver circuit, and it is possible to increase a voltage to be applied to a drive coil.

A logic cell including a fixed assembly including a first electrode, a mobile assembly including a second electrode, and third, fourth, and fifth electrodes, wherein: the first, second, third, fourth, and fifth electrodes are insulated from one another; the first and second electrodes define a capacitor variable according to the position of the mobile assembly relative to the fixed assembly; the third electrode is connected to a node of application of a first logic input signal; the fourth electrode is connected to a node of application of a second logic input signal; the fifth electrode is connected to a reference node; and the position of the second electrode relative to the first electrode is a function of a combination of the first and second logic input signals.

A logic cell including a fixed assembly including a first electrode, a mobile assembly including a second electrode, and third, fourth, and fifth electrodes, wherein: the first, second, third, fourth, and fifth electrodes are insulated from one another; the first and second electrodes define a capacitor variable according to the position of the mobile assembly relative to the fixed assembly; the third electrode is connected to a node of application of a first logic input signal; the fourth electrode is connected to a node of application of a second logic input signal; the fifth electrode is connected to a reference node; and the position of the second electrode relative to the first electrode is a function of a combination of the first and second logic input signals.

An oscillator circuit includes a first integrator unit to charge a first capacitor at a first integration node, a second integrator unit to charge a second capacitor at a second integration node, a chopped comparator unit and a logic unit. The chopped comparator unit includes comprises a switching unit, a sensing comparator and a replica comparator. The switching unit is configured to couple the first integration node, the second integration node and a reference voltage VREF to the sensing comparator and the replica comparator, depending upon a phase determined by a first input clock signal C1 and a second input clock signal C2, which have opposite phases. The logic unit is configured to generate signals C1, C2, D1, D2, E1, E2 for controlling each integrator unit.