A circuit, comprising a trapezoidal generator that comprises digital logic configured to couple at a first input to a loop controller and at a second input to a buck-boost region detector and a driver coupled to an output of the digital logic and configured to couple to at least one power transistor of a power converter.

A signal calculator includes a capacitor and a variable current source. The variable current source charges the capacitor and generates a current corresponding to a predetermined voltage during a first period. A first voltage is generated using a voltage of the capacitor charged during an enable period of a first signal in the first period, and a second voltage is generated using a voltage of the capacitor charged during the first period. The variable current source further generates a current corresponding to the second voltage during a second period. A second signal is generated according to a result of comparing the first voltage with the voltage of the capacitor during the second period, and a fourth voltage is generated by generating and sampling a third voltage which is increased according to a first current during an enable period of the second signal in the second period.

A signal output circuit is configured to control driving of an output transistor to output a trapezoidal wave output signal from a main terminal of the output transistor. The signal output circuit includes a driver that drives the output transistor at a constant current and a drive capability changing unit that periodically changes drive capability of the driver.

A signal output circuit is configured to control driving of an output transistor to output a trapezoidal wave output signal from a main terminal of the output transistor. The signal output circuit includes a driver that drives the output transistor at a constant current and a drive capability changing unit that periodically changes drive capability of the driver.

A circuit, comprising a trapezoidal generator that comprises digital logic configured to couple at a first input to a loop controller and at a second input to a buck-boost region detector and a driver coupled to an output of the digital logic and configured to couple to at least one power transistor of a power converter.

A circuit, comprising a trapezoidal generator that comprises digital logic configured to couple at a first input to a loop controller and at a second input to a buck-boost region detector and a driver coupled to an output of the digital logic and configured to couple to at least one power transistor of a power converter.

Embodiments herein relate to a pulse generator which provides first and second clock pulses to one or more pulsed latches, where the pulse generator replicates a delay of the pulsed latches in providing the first and second clock pulses. The pulse generator can include a replica of latch components in the pulsed latches such as a tri-state inverter, a transmission gate and inverters, where an output of the tri-state inverter is coupled to the transmission gate and to an input of the inverter, and an output of the inverter is coupled to an input of the tri-state inverter. The tri-state inverter can be a modified tri-state inverter with an output forced to 1 when a clock signal is 0. In one approach, the latch components of the pulse generator are to write a logic 1 when a clock signal goes high.

Embodiments herein relate to a pulse generator which provides first and second clock pulses to one or more pulsed latches, where the pulse generator replicates a delay of the pulsed latches in providing the first and second clock pulses. The pulse generator can include a replica of latch components in the pulsed latches such as a tri-state inverter, a transmission gate and inverters, where an output of the tri-state inverter is coupled to the transmission gate and to an input of the inverter, and an output of the inverter is coupled to an input of the tri-state inverter. The tri-state inverter can be a modified tri-state inverter with an output forced to 1 when a clock signal is 0. In one approach, the latch components of the pulse generator are to write a logic 1 when a clock signal goes high.

A circuit, comprising a trapezoidal generator that comprises digital logic configured to couple at a first input to a loop controller and at a second input to a buck-boost region detector and a driver coupled to an output of the digital logic and configured to couple to at least one power transistor of a power converter.

A circuit, comprising a trapezoidal generator that comprises digital logic configured to couple at a first input to a loop controller and at a second input to a buck-boost region detector and a driver coupled to an output of the digital logic and configured to couple to at least one power transistor of a power converter.