A load drive circuit is configured to control driving of an electric load that is a direct current load, and includes a controller, a switching element, and a current detection portion. The controller generates and outputs a control signal for controlling a flowing state of a load current that flows to the electric load. The switching element switches flowing and interrupting of the load current based on the control signal. The current detection portion detects the load current. The controller includes a type determination portion and a control signal output portion. The type determination portion determines a type of the electric load based on the load current detected by the current detection portion. The control signal output portion generates and outputs the control signal based on the type determined by the type determination portion.

A load drive circuit is configured to control driving of an electric load that is a direct current load, and includes a controller, a switching element, and a current detection portion. The controller generates and outputs a control signal for controlling a flowing state of a load current that flows to the electric load. The switching element switches flowing and interrupting of the load current based on the control signal. The current detection portion detects the load current. The controller includes a type determination portion and a control signal output portion. The type determination portion determines a type of the electric load based on the load current detected by the current detection portion. The control signal output portion generates and outputs the control signal based on the type determined by the type determination portion.

The present technology relates to an image pickup device and an electronic apparatus capable of preventing degradation of the picture quality. A plurality of current sources can be selectively connected to an output terminal for outputting a reference signal having a level that varies, and a plurality of terminating resistors are connected to the output terminal. The terminating resistors that are to supply current of current sources that are connected to the output terminal are connected by a plurality of switches, and current of current sources that are not connected to the output terminal is supplied to the switches. The present technology can be applied, for example, to image pickup devices that perform AD conversion using a reference signal and so forth.

A drive waveform setting unit sets a drive waveform of a drive signal, and a drive current is applied to a drive coil provided in a response force generation mechanism in accordance with the drive waveform. The drive waveform has a first drive section in which a signal intensity increases linearly and a second drive section including a peak. An increase rate of the signal intensity in the second drive section is lower than that in the first drive section. As a result, it is easy to follow the frequency characteristics of a driver circuit, and it is possible to increase a voltage to be applied to a drive coil.

A logic cell including a fixed assembly including a first electrode, a mobile assembly including a second electrode, and third, fourth, and fifth electrodes, wherein: the first, second, third, fourth, and fifth electrodes are insulated from one another; the first and second electrodes define a capacitor variable according to the position of the mobile assembly relative to the fixed assembly; the third electrode is connected to a node of application of a first logic input signal; the fourth electrode is connected to a node of application of a second logic input signal; the fifth electrode is connected to a reference node; and the position of the second electrode relative to the first electrode is a function of a combination of the first and second logic input signals.

A drive circuit which drives a capacitive load on the basis of a drive signal output from a node includes a first wire; a second wire; an amplification unit; a capacitor and a resistance element; a determination unit which determines whether or not a voltage of a differentiated drive signal is within a predetermined range in case where a magnitude of a voltage change of the signal is less than or equal to a threshold; and a voltage output unit which amplifies the a voltage of the signal by a predetermined multiple, for example, one time, and outputs the amplified signal toward the node in a case where it is determined that the voltage of the differentiated drive signal is within the predetermined range.

A drive circuit which drives a capacitive load on the basis of a drive signal output from a node includes a first wire; a second wire; an amplification unit; a capacitor and a resistance element; a determination unit which determines whether or not a voltage of a differentiated drive signal is within a predetermined range in case where a magnitude of a voltage change of the signal is less than or equal to a threshold; and a voltage output unit which amplifies the a voltage of the signal by a predetermined multiple, for example, one time, and outputs the amplified signal toward the node in a case where it is determined that the voltage of the differentiated drive signal is within the predetermined range.

A system and method for synchronizing clocks. The system may include a master device having a reference clock and slave devices whose clocks may be synchronized with the reference clock. The master device may drive a light transmitter (e.g., LED) to produce a light pulse with each clock cycle of the reference clock. The light pluses may be distributed by a transmissive medium, such as a low cost optical fiber.

A system and method for synchronizing clocks. The system may include a master device having a reference clock and slave devices whose clocks may be synchronized with the reference clock. The master device may drive a light transmitter (e.g., LED) to produce a light pulse with each clock cycle of the reference clock. The light pluses may be distributed by a transmissive medium, such as a low cost optical fiber.

An adaptive control circuit of SRAM (Static Random Access Memory) includes a switch circuit, a forward diode-connected transistor, a backward diode-connected transistor, and a first delay circuit. The switch circuit is supplied by a supply voltage, and is coupled to a first node. The backward diode-connected transistor is coupled in parallel with the forward diode-connected transistor between the first node and a second node. The first delay circuit is coupled between the second node and a ground voltage.