A clock sending apparatus and method, and a clock receiving apparatus and method are disclosed. The clock sending apparatus may include, an input unit configured to input a first and second input clocks; a sampling unit configured to acquire a first and second sampling clocks, and determine a first frequency control word according to the first and second sampling clocks, the first frequency control word is indicative of a relationship between the first and second sampling clocks, the first sampling clock is determined by the first input clock according to a preset rule, and the second sampling clock is determined by the second input clock according to a preset rule; and a sending unit configured to generate a clock signal according to the first input clock and send the clock signal that carries at least the first frequency control word to a receiving side.

A radio-frequency (RF) to direct current (DC) converter is provided. When a DC electrical current is applied via a DC input port of the converter, the DC electrical current is shunted to ground through a Josephson junction (JJ) of the converter and substantially no DC electrical current flows through a resistor of the converter, and when an RF electrical current is applied via an RF input port of the converter, output trains of SFQ current pulses from a DC to SFQ converter of the RF-to-DC converter with pulse-to-pulse spacing inversely proportional to the RF electrical current frequency cause the JJ to switch at a rate commensurate with an RF frequency of the RF electrical current to generate a steady state voltage across the JJ linearly dependent on the RF frequency.

In an embodiment a radiofrequency doubler includes a first transistor and a second transistor connected in parallel between a first differential output and a first terminal of a current source configured to provide a bias current, a second terminal of the current source being connected to a first supply potential, a third transistor connected between the first terminal of the current source and a second differential output, a circuit configured to apply an AC component of a first differential input and a first DC voltage to a gate of the first transistor, apply an AC component of a second differential input and the first DC voltage to a gate of the second transistor and apply a second DC voltage to a gate of the third transistor, and a feedback loop configured to control the first voltage or the second voltage from a difference between DC components of the first and second differential outputs so as to equalize the DC components.

According to one implementation of the present disclosure, a circuit includes: two or more metal wires, respective XOR gates coupled to each of the two or more top metal wires, a shift register having outputs coupled to the XOR gates, an OR gate configured to receive each of the outputs of the XOR gates, and a latch configured to receive an output of the OR gate and transmit an output signal corresponding to an alarm signal.

The present embodiment relates to an oscillator circuit, a semiconductor integrated circuit device and a method for frequency correction of an oscillator circuit, and more particularly, to an oscillator circuit, a semiconductor integrated circuit device and a method for frequency correction of an oscillator circuit capable of stably maintaining an output frequency of a clock signal even when a temperature of the semiconductor integrated circuit device changes.

A method includes performing a duty-cycle correction. The method can include inputting a signal to a duty-cycle correction circuit. The method can further include transferring the signal through an alternating current-coupling (AC-coupling) component of the duty-cycle correction circuit. The method can further include transferring the signal through a feedback circuit, wherein the feedback circuit comprises a plurality of resistors. The method can further include outputting a signal that includes a corrected duty-cycle with a particular amount of duty-cycle distortion.

A method includes performing a duty-cycle correction. The method can include inputting a signal to a duty-cycle correction circuit. The method can further include transferring the signal through an alternating current-coupling (AC-coupling) component of the duty-cycle correction circuit. The method can further include transferring the signal through a feedback circuit, wherein the feedback circuit comprises a plurality of resistors. The method can further include outputting a signal that includes a corrected duty-cycle with a particular amount of duty-cycle distortion.

A communication circuit is disclosed. The communication circuit includes a clock input, and a clock divider configured to generate an output clock signal having a fundamental frequency which is substantially equal to a fundamental frequency of an input clock signal received at the clock input divided by a factor of (2N+1)/2N, where the clock divider is configured to generate 2N+1 pre-aligned phase shifted clock signals based at least in part on the input clock signal, generate 2N unique phase shifted clock signals based at least in part on the 2N+1 pre-aligned phase shifted clock signals, where the 2N unique phase shifted clock signals are substantially separated in phase by 360/2N degrees, and generate the output clock signal based at least in part on the 2N unique phase shifted clock signals, and a mixer, configured to receive the output clock signal.

A low-power clock generation circuit has a phase generator that receives an input clock signal and uses the input clock signal to generate multiple intermediate clock signals with different phase shifts, a phase rotator circuit that outputs phase-adjusted clock signals, a frequency doubler circuit that receives a plurality of the phase-adjusted clock signals and outputs two frequency-doubled clock signals having a 180° phase difference, and a quadrature clock generation circuit that receives the two frequency-doubled clock signals and provides four output signals that include in-phase and quadrature versions of the two frequency-doubled clock signals.

An apparatus comprising a local oscillator (LO) for driving a mixer, the LO being configured to oscillate at an oscillation frequency, and generate a first set of LO signals, wherein each of the first set of LO signals has a LO signal frequency equal to a first multiplication factor m multiplied by the oscillation frequency, the first multiplication factor m, being an integer greater than or equal to two, and each of the first set of LO signals is separated by adjacent LO signals by a phase difference equal to 360° divided by a first variable n, the first variable n being an integer that is greater than or equal to two.