The present invention provides a fractional frequency divider, wherein the fractional frequency divider includes a plurality of registers, a counter, a control signal generator and a clock gating circuit. Regarding the plurality of registers, at least a portion of the registers are set to have values The counter is configured to sequentially generate a plurality of counter values, wherein the plurality of counter values correspond to the at least a portion of the registers, respectively, and the plurality of counter values are generated repeatedly The control signal generator is configured to generate a control signal based on the received counter value and the value of the corresponding register. The clock gating circuit is configured to refer to the control signal to mask or not mask an input clock signal to generate an output clock signal.

A system may include a driver circuit configured to receive a clock signal. The system may also include a first tuned circuit and a second tuned circuit. The first tuned circuit and the driver circuit may be collectively tuned according to a first frequency range. The first tuned circuit may be configured to be active when a rate of the clock signal is within the first frequency range and to be inactive when the rate is outside of the first frequency range. Further, the second tuned circuit and the driver circuit may be collectively tuned according to a second frequency range that is different from the first frequency range. The second tuned circuit may be configured to be active when the rate is within the second frequency range and to be inactive when the rate is outside of the second frequency range.

Apparatuses and methods of widespread equispatiated phase generation of a clock divided by a non-integer factor are described. One integrated circuit includes a clock divider and a phase generator. The clock divider receives a single-phase clock signal from a clock source and generates a divided clock signal. The phase generator receives the divided clock signal and the single-phase clock signal and generates multiple phase signals using the divided clock signal and the single-phase clock signal. The phase signals are equispatiated.

Transmitters having increased efficiency, such as may be useful in millimeter-wave devices. A semiconductor device, comprising a transmitter, comprising a modulator configured to receive a differential input signal having a first frequency and provide a differential modulated signal having the first frequency and a first clock phase; a series comprising one or more frequency multipliers, wherein the series of frequency multipliers is configured to receive the differential modulated signal and provide a differential second signal having a second frequency greater than the first frequency and having a second clock phase; and an output transformer configured to receive the differential second signal and transform the differential second signal to a single-ended output signal. Methods of using such transmitters. Systems for manufacturing devices comprising such transmitters.

Circuits and processes for locking a voltage-controlled oscillator (VCO) at a high frequency signal are described. A circuit may include an adjustable current converter (ACC), coupled at an input terminal to a power source, operable to output a control signal (VC) at an output terminal. A first switch may be coupled to the ACC and to the VCO. The VCO, when in an “ON” state, receives the control signal and outputs a high frequency signal (VHF). A digital filter may be coupled to the VCO and operable to receive the VHF. Based on the VHF, the digital filter generates a data signal having a data value. The circuit may also include a digital-to-analog converter (DAC) operable to receive the data signal and, based on the data value, output an adjustment signal to the ACC. The ACC may adjust the control signal based on the adjustment signal received from the DAC.

This disclosure describes apparatuses, methods, and techniques for implementing a multimode frequency multiplier. In example implementations, an apparatus for generating a frequency includes a multimode frequency multiplier. The multimode frequency multiplier includes a multiphase generator and a reconfigurable frequency multiplier. The multiphase generator is configured to produce a first signal including multiple phase components and having a first frequency. The reconfigurable frequency multiplier is coupled in series with the multiphase generator. The reconfigurable frequency multiplier is configured to produce a second signal based on the first signal and having a second frequency that is a multiple of the first frequency.

A clock generator includes a pulse generator and a duty cycle correction circuit. The pulse generator is configured to receive an input clock signal and generate a pulse signal according to the input clock signal. The duty cycle correction circuit, coupled to the pulse generator, is configured to adjust a duty cycle of the pulse signal to generate an output clock signal.

A device for generating first clock signals includes first circuits, each including a ring oscillator delivering one of the first clock signals and being connected to a first node configured to receive a first current. A circuit selects one the first clock signals, and a phase-locked loop delivers a second signal which is a function of a difference between a frequency of the first selected clock signal and a set point frequency. Each first circuit supplies the first node with a compensation current determined by the second signal, when this first circuit delivers the selected clock signal and operates in controlled mode.

A method is disclosed for producing an output clock signal with a target frequency using an oscillator circuit portion configured to receive a control value and produce an output clock signal with a frequency dependent on the control value. In one embodiment, the method comprises providing a first control value to the oscillator circuit portion corresponding to the target frequency, so as to cause the oscillator circuit portion to produce the output clock signal with a first frequency, comparing the output clock signal with a reference clock signal having a reference frequency to determine an offset between the first frequency and the target frequency, and providing a second control value to the oscillator circuit portion that differs from the first control value by a magnitude calculated with reference to the determined offset, to cause the oscillator circuit portion to produce the output clock signal with a second frequency.

A local oscillator (LO) circuit includes a voltage controlled oscillator (VCO) configured to receive an output of a phase locked loop (PLL) circuit, the VCO coupled to a clock gating circuit configured to generate a VCO output signal (vco_g), a local oscillator (LO) divider configured to receive the VCO output signal (vco_g) and a local oscillator (LO) preset signal, the LO preset signal configured to set the LO divider to a predetermined initial phase, a programmable divider configured to receive a divider signal and the VCO output signal (vco_g) and generate a local oscillator (LO) phase detection trigger signal, Fv, a toggling accumulator coupled to an output of the programmable divider, the toggling accumulator configured to receive the divider signal and the LO phase detection trigger signal, Fv, and generate a counter signal, and a decision logic configured to receive a sample enable signal and the counter signal and adjust the programmable divider based on the sample enable signal and the counter signal.