The present invention relates to the technical field of printing in particular, to a frequency multiplication method and device, for solving the problem of poor quality of a printed image. One method comprises: for two adjacent pulse signals output from an encoder, determining a first kind of pulse signals and a second kind of pulse signals to be inserted between the two adjacent pulse signals according to a time interval between the two adjacent pulse signals and a frequency multiplication value corresponding to a longitudinal resolution; determining a period of the first kind of pulse signals to be inserted between the two adjacent pulse signals, and determining a period of the second kind of pulse signals to be inserted between the two adjacent pulse signals; and performing frequency multiplication processing on the two adjacent pulse signals. The embodiments of the invention further improve the printing quality of images.

A transformer-less DFM device comprising: an input receiving signals that are an integer multiple of an input signal; an edge detector that provides a quantized or a state output comparing an the input signal to a feedback signal; a statemachine that has counters and decimation circuits to provide a digitized output to a DAC that tunes delays between the input/output signals; a DLL for generating delay signals from the input signal that form an input to an edge combiner wherein the edge combiner takes different phases from the DLL to generate a multiplied output signal; a first DAC that takes the signal from the statemachine and provide a control to a supply circuit of the DLL to adjust a delay through a supply voltage; a second DAC that takes a signal from the statemachine and provides control to a backgate circuit of the DLL to adjust the delay.

A semiconductor integrated circuit includes a first circuit and a second circuit. The first circuit is configured to divide a first pulse signal having a first duty cycle by N (where N is an integer of 2 or more), and output 2×N second pulse signals of which phases are different from each other. The first pulse signal is a pair of differential signals. The second circuit is configured to receive one or more selection signals and calculate a logical product of one of the one or more selection signals and two of the 2×N second pulse signals to generate a third pulse signal having a second duty cycle less than the first duty cycle.

The clock generation circuit outputs a clock signal with a constant cycle by repeating the following operations: when an enable signal becomes a H level, the clock signal immediately rises, and a sense end is changed to a L level via a first capacitor, then a voltage of the sense end is gradually increased via a resistor, and when the sense end reaches a predetermined potential, an output of a second inverter becomes the L level, the clock signal becomes the L level, an inverted clock signal becomes the H level, and accordingly the sense end becomes the H level; and thereafter, a current flows via the resistor so that the voltage of the sense end decreases gradually, when the sense end reaches a predetermined potential, the output of the second inverter becomes a H level, the clock signal becomes the H level, the sense end is changed to a L level via the first capacitor, then the voltage of the sense end is gradually increased via the resistor, and when the sense end reaches a predetermined potential, the output of the second inverter becomes the L level and the clock signal becomes the L level.

A predictive clock controller is provided for modifying the frequency of a clock signal provided to a processing unit based on knowledge of the power usage by the application running on the processing unit during different execution periods. The predictive clock controller counts barrier syncs for the application, so as to determine where the application is in its sync schedule. The predictive clock controller is able to determine from the number of counted syncs, when the application will transition from one execution period to another execution period with different power requirements, and to adjust the clock frequency accordingly.

Embodiments of the present disclosure provide systems and methods of reducing the EMI effect generated by such analog blocks. By varying the clock frequency in time of oscillators used by such analog blocks, the EMI energy may be spread over a wide spectrum range thereby reducing the peak energy for the main frequency. To achieve this, the oscillator frequency is directly varied using analog mechanisms. The mechanisms may be based on a synchronized method for increasing/decreasing the current that is charging/discharging the oscillator capacitor. The frequency variation may be achieved by analog control of the extra charge/discharge current.

A method of frequency doubling includes receiving a first clock that has a fifty percent duty cycle and is a two-phase clock having a first phase and a second phase; outputting a second clock using a multiplexer by selecting one of the first phase and the second phase of the first clock in accordance with a third clock; delaying the second clock into a fourth clock using a recirculating delay circuit; and using a divide-by-two circuit to output the third clock in accordance with the fourth clock.

A method and apparatus for saving power in integrated circuits is disclosed. An IC includes functional circuit blocks which are not placed into a sleep mode when idle. A power management circuit may monitor the activity levels of the functional circuit blocks not placed into a sleep mode. When the power management circuit detects that an activity level of one of the non-sleep functional circuit blocks is less than a predefined threshold, it reduce the frequency of a clock signal provided thereto by scheduling only one pulse of a clock signal for every N pulses of the full frequency clock signal. The remaining N−1 pulses of the clock signal may be inhibited. If a high priority transaction inbound for the functional circuit block is detected, an inserted pulse of the clock signal may be provided to the functional unit irrespective of when a most recent regular pulse was provided.

Described are apparatus and methods for high frequency clock generation. A circuit includes a phase frequency detector (PFD) which outputs differential error clocks based on comparison of differential reference clocks and differential feedback clocks, which are at a first frequency. A controlled oscillator (CO) connected to the PFD, which adjusts a frequency of the CO based on the differential error clocks to generate differential clocks at a second frequency, which is a multiple of the first frequency. A quadrature clock generator connected to the CO, which generates differential quadrature clocks at the second frequency from the differential clocks, where the differential feedback clocks are generated from the differential clocks and one pair of the differential quadrature clocks. A frequency doubler which doubles each pair of the differential quadrature clocks and outputs fully differential and balanced clocks at a third frequency for distribution, which is a multiple of the second frequency.

A pulse current generation circuit (100) for neural stimulation includes an analogue signal receiving device (101) for receiving an analogue signal; an analogue-to-digital converter (102) for converting the analogue signal into a digital control signal; a current signal controller (103) for producing, according to the digital control signal, pulse current parameters for generating bidirectional pulse current signals; and a current generator (104) for generating, according to the pulse current parameters, bidirectional pulse current signals for neural stimulation, and the current generator can generate pulse currents of different precisions according to the pulse current parameters. In addition, the present invention further relates to a charge compensation circuit, a charge compensation method, and an implantable electrical retina stimulator using the pulse current generation circuit or the charge compensation circuit.