A divider circuit includes a subtract-by-two circuit receiving MSBs of an input and producing a subtracted-by-two output, a subtract-by-one circuit receiving the MSBs and producing a subtracted-by-one output, a first multiplexer passing the subtracted-by-two or the subtracted-by-one output based on a first control signal, a second multiplexer passing output of the first multiplexer or the MSBs based on a second control signal to produce an asynchronous divisor. An asynchronous one-shot N+2 divider divides an input clock by the asynchronous divisor to produce a first divided signal. An output flip-flop receives the first divided signal and is clocked by an inverse of the input clock to produce a second divided signal. A third multiplexer passes the first divided signal or the second divided signal in response to a select load signal to produce a multiplexer output. A divider divides the multiplexer output by a set divisor to produce an output clock.

An apparatus includes a phase modulator configured to modulate a phase of an incoming frequency-modulated signal based on a clock signal to generate a phase-modulated signal, where the clock signal is associated with a clock frequency. The apparatus also includes an etalon configured to receive the phase-modulated signal and generate an output signal based on the phase-modulated signal. The apparatus further includes a detector configured to identify amplitudes associated with a first harmonic of the clock frequency and a first subharmonic of the clock frequency in the output signal. In addition, the apparatus includes a decoder configured to recover information encoded in the incoming frequency-modulated signal based on instantaneous frequency deviations of the incoming frequency-modulated signal, where the instantaneous frequency deviations are identified based on relative amplitudes of the first harmonic and the first subharmonic.

An apparatus can implement a frequency doubler with duty cycle correction in conjunction with, for instance, a phase-locked loop (PLL) to decrease phase noise. In an example aspect, an apparatus has a frequency doubler including a signal combiner, a first signal pathway, and a second signal pathway. The frequency doubler also includes a doubler input node and a doubler output node. The signal combiner is coupled to the doubler output node. The first signal pathway is coupled between the doubler input node and the signal combiner and includes a first adjustable delay cell. The second signal pathway is also coupled between the doubler input node and the signal combiner and includes a second adjustable delay cell.

An odd harmonic generation device is provided. The odd harmonic generation device includes an even harmonic generation unit and a mixer. In this context, the even harmonic generation unit is configured to generate two even harmonic signals on the basis of a fundamental signal. In addition to this, the mixer is configured to mix the fundamental signal with the two even harmonic signals to generate a desired odd harmonic signal.

A modulator spreads the spectrum of a generated clock to reduce Electro-Magnetic Interference (EMI). A capacitor is charged by a variable current to generate a ramp voltage that is compared to a reference to end a clock cycle and discharge the capacitor. An up-down counter drives a Digital-to-Analog Converter (DAC) that controls the variable charging current to provide triangle modulation. A smaller offset current is added or subtracted for cubic modulation when the up-down counter reaches its minimum count. A frequency divider that clocks the up-down counter also clocks a Linear-Feedback Shift-Register (LFSR) to that controls pseudo-random current sources that further modulate variable current and frequency. The LFSR is clocked with the up-down counter to modulate each frequency step, or only at the minimum count to randomly modulate at the minimum frequency. Binary-weighted bits from the up-down counter to the DAC are swapped to modulate the frequency step size.

A clock multiplexer device includes first and second control circuitries and an output circuitry. The first control circuitry generates a first enable signal and a first signal according to a first clock signal and a first selection signal, and determines whether to output the first signal to be a first output clock signal according to a second selection signal and a second enable signal. The first and the second selection signals have opposite logic values. The second control circuitry generates the second enable signal and a second signal according to a second clock signal and the second selection signal, and determines whether to output the second signal to be a second output clock signal according to the first selection signal and the first enable signal. The output circuitry outputs one of the first output clock signal and the second output clock signal to be a final clock signal.

A digital circuit device includes a power supply circuitry, a digital circuitry, a digital circuitry, and a protection circuitry. The power supply circuitry is configured to output a supply voltage. The digital circuitry is configured to be driven by the supply voltage, and is configured to perform at least one operation according to a first clock signal. The protection circuitry is configured to generate the first clock signal according to at least one of a voltage drop of the supply voltage and a load signal sent from the digital circuitry.

In the oscillator, a quartz crystal resonator and an oscillation circuit formed in an IC incorporating an inductor are electrically coupled to each other with a resonator interconnection disposed on a surface of a substrate to form an oscillation loop. A conductor layer disposed as an intermediate layer of the substrate is disposed so as to overlap the resonator interconnection and not to overlap the inductor incorporated in the IC in a plan view.

A digital phase-frequency detector characterizes a delay between two input clock signals using a ring oscillator. A cycle count of a ring oscillator signal circulating through a loop in the ring oscillator during the delay provides a coarse measurement of the delay. A phase of the ring oscillator signal in the loop at the end of the delay provides a fine measurement of the delay. A digital phase-locked loop may control an oscillation frequency of a digitally-controlled oscillator responsive to the fine measurement of the delay and control a division within a clock divider responsive to the coarse measurement of the delay.

A single flux quantum (SFQ) circuit includes a radio frequency (RF) to direct current (DC) conversion stage. A DC to RF current conversion stage is coupled to a single output of the RF to DC conversion stage. The DC to RF current conversion stage includes a plurality of series stacked Josephson Junctions (JJs) having n stages, configured to convert a DC current received from the RF to DC conversion stage and reconvert the DC current to an RF tone.