Embodiments of methods and systems for attenuator phase compensation are described. In an embodiment, a method for attenuator phase compensation involves determining a phase compensation value for an attenuator based on an attenuation configuration of the attenuator and performing phase compensation according to the phase compensation value to maintain a constant phase response.

A vector sum circuit and a phase controller including the vector sum circuit are provided. The vector sum circuit includes an amplifier configured to amplify an input orthogonal signal by using a first metal oxide semiconductor field effect transistor (MOSFET), and a self body-biasing circuit comprising a resistor. The self body-biasing circuit is configured to connect a drain and a body of the first MOSFET to reduce a voltage connected to the body as a current at the drain increases.

Power combiners having increased output power, such as may be useful in millimeter-wave devices. The power combiner comprise at least two channels, wherein each channel comprises a phase alignment circuit, wherein the phase alignment circuit comprises a first differential input subcircuit comprising a first inverter and a second inverter, and a second differential input subcircuit comprising a third inverter and a fourth inverter, wherein the first inverter, the second inverter, the third inverter, and the fourth inverter each comprise a PMOS transistor and an NMOS transistor each having an adjustable back gate bias voltage. By adjusting the back gate bias voltage, the phases of the signal through each channel may be aligned, which may increase the output power of the power combiner. Methods of increasing output power of such power combiners. Systems for manufacturing devices comprising such power combiners.

Apparatuses and methods for providing voltages to conductive lines between which clock signal lines are disposed are disclosed. Voltages provided to the conductive lines may provide voltage conditions for clock signals on the clock signal lines that are relatively the same for at least some of the clock edges of the clock signals. Having the same voltage conditions may mitigate variations in timing/phase between the clock signals due to different voltage influences when a clock signal transitions from a low clock level to a high clock level.

An apparatus includes a plurality of coarse delay circuits and a phase blender circuit. The coarse delay circuits may be configured to (i) receive an input clock signal, (ii) receive a plurality of control signals and (iii) generate a first phase signal and a second phase signal. The phase blender circuit may be configured to (i) receive the first phase signal and the second phase signal, (ii) receive a phase control signal, (iii) step between stages implemented by the coarse delay circuits and (iv) present an output clock signal. The phase blender circuit may mitigate a mismatch between the stages of the coarse delay circuits by interpolating an amount of coarse delay provided by the coarse delay circuits.

Duty cycle correction devices for static compensation of an active clock edge shift. A duty cycle correction circuit in the duty cycle correction device corrects a clock input signal, according to a first control signal. A programmable delay circuit or a modified duty cycle correction circuit in the duty cycle correction device compensates a shift of an active clock edge in a clock output signal of the duty cycle correction circuit, according to a second control signal. A mapping circuit in the duty cycle correction device generates the second control signal by mapping a digital value of the first control signal and a digital value of the second control signal.

A direct drive circuit for providing RF power to a component of a substrate processing system includes a clock generator to generate a clock signal at a first frequency, a gate driver to receive the clock signal and a half bridge circuit. The half bridge circuit includes a first switch with a control terminal connected to the gate driver, a first terminal and a second terminal; a second switch with a control terminal connected to the gate driver, a first terminal connected to the second terminal of the first switch and an output node, and a second terminal; a first DC supply to supply a first voltage to the first terminal of the first switch; and a second DC supply to supply a second voltage to the second terminal of the second switch. The first and the second voltages have opposite polarities and are approximately equal in magnitude.

An apparatus is configured to receive a two-phase input clock and output a four-phase output clock. The apparatus includes a circuit configured in a ring topology comprising a first switch controlled by a first phase of the input clock, a first inverting amplifier, a second switch controlled by a second phase of the input clock, a second inverting amplifier, a third switch controlled by the first phase of the input clock, a third inverting amplifier, a fourth switch controlled by the second phase of the input clock, and a fourth inverting amplifier, wherein the first inverting amplifier and the third inverting amplifier share a first regenerative load that is reset upon the first phase of the input clock, and the second inverting amplifier and the fourth inverting amplifier share a second regenerative load that is reset upon the second phase of the input clock.

Various aspects provide for error detection and compensation for a multiplexing transmitter. For example, a system can include an error detector circuit and a duty cycle correction circuit. The error detector circuit is configured to measure duty cycle error for a clock associated with a transmitter to generate error detector output based on a clock pattern for output generated by the transmitter in response to a defined bit pattern. The duty cycle correction circuit is configured to adjust the clock associated with the transmitter based on the error detector output. Additionally or alternatively, the error detector circuit is configured to measure quadrature error between an in-phase clock and a quadrature clock in response to the defined bit pattern. Additionally or alternatively, the system can include a quadrature error correction circuit configured to adjust phase shift between the in-phase clock and the quadrature clock based on quadrature error.

A data receiving circuit may include: a variable delay circuit suitable for generating a delayed strobe signal by delaying a strobe signal; a receiving circuit suitable for sampling data in synchronization with the delayed strobe signal; a phase shift circuit suitable for generating a shifted strobe signal by shifting a phase of the delayed strobe signal; a phase comparison circuit suitable for comparing phases of the data and the shifted strobe signal; and a delay adjusting circuit suitable for adjusting a delay value of the variable delay circuit in response to the phase comparison result of the phase comparison circuit.