A power amplifier circuit includes: a first differential amplifier that amplifies a first signal split from the input signal and outputs a second signal; a second differential amplifier that amplifies a third signal split from the input signal and outputs a fourth signal; a first transformer including a first input-side winding to which the second signal is input and a first output-side winding; a second transformer including a second input-side winding to which the fourth signal is input and a second output-side winding; a first phase conversion element that is connected in parallel with the first output-side winding and outputs a fifth signal; and a second phase conversion element that is connected in parallel with the second output-side winding and outputs a sixth signal. The first and second output-side windings are connected in series and output a signal obtained by adding voltages of the fifth and sixth signals together.

Embodiments described herein provide a method of separating a liquid mixture, comprising providing a liquid mixture to a separator, electrically coupling a power circuit to the liquid mixture inside the separator, applying a time-varying voltage to the power circuit, detecting a phase angle in the power circuit; and controlling the phase angle by adjusting a characteristic of the time-varying voltage.

A phase mixing circuit for a multi-phase signal includes a jitter cancellation circuit configured to mix phases of a signal input to a first node and a signal input to a second node to produce signals at a third node and a fourth node; and a delay adjustment circuit configured to adjust delays of the signals output from the third node and the fourth node to produce signals at a fifth node and a sixth node.

In described examples, a quadrature phase shifter includes digitally programmable phase shifter networks for generating leading and lagging output signals in quadrature. The phase shifter networks include passive components for reactively inducing phase shifts, which need not consume active power. Output currents from the transistors coupled to the phase shifter networks are substantially in quadrature and can be made further accurate by adjusted by a weight function implemented using current steering elements. Example low-loss quadrature phase shifters described herein can be functionally integrated to provide low-power, low-noise up/down mixers, vector modulators and transceiver front-ends for millimeter wavelength (mmwave) communication systems.

Embodiments disclosed herein generally relate to electronic devices, and more specifically, to a waveform generation circuit for input devices. One or more embodiments provide a new waveform generator for an integrated touch and display driver (TDDI) and methods for generating a waveform for capacitive sensing with a finely tunable sensing frequency. A waveform generator includes accumulator circuitry, truncation circuitry, and saturation circuitry. The accumulator circuitry is configured to accumulate the phase increment value based on a clock signal, and output the accumulated phase increment value. The truncation circuitry configured to drop one or more bits of the accumulated phase increment value to output a truncated value. The saturation circuitry is configured to compare the truncated value to a saturation limit and output a signal corresponding to accessed data samples.

A method for in-phase (I) and quadrature (Q) signal generation is disclosed. The method may include a first stage receiving a differential input signal. The first stage may also generate first differential in-phase and quadrature output signals, which may be sent by the first stage to a second stage. The second stage may generate second differential in-phase and quadrature output signals, which may have amplitude and phase mismatches less than an amplitude and phase mismatches of the first differential output signals. The second stage may then output the second differential I/Q output signals.

The present disclosure provides a comparator, an integrated circuit, and a method. One form of the comparator includes: a first mirror unit, configured to output a dynamic current to an input unit and adjust a value of the dynamic current based on a received feedback current; a second mirror unit, configured to output a fixed current to the input unit; the input unit, configured to output a first current to a feedback unit and a second current to an output unit based on a difference between a first voltage and a second voltage, the fixed current, and the dynamic current; the feedback unit, configured to output a feedback current to the first mirror unit after receiving the first current; and the output unit, configured to: obtain the second current or a mirror current of the adjusted dynamic current, output a first comparison result in response to the second current when the first voltage is greater than the second voltage, and output a second comparison result in response to the mirror current when the first voltage is less than the second voltage. The comparator can improve a comparison speed.

A circuit and method are provided for improving the accuracy of a quadrature clock. The method includes receiving a first phase, a second phase, a third phase, and a fourth phase of a first quadrature clock; outputting a first phase of a second quadrature clock in accordance with an equal sum of the first phase and the second phase of the first quadrature clock using a first summing network; outputting a second phase of the second quadrature clock in accordance with an equal sum of the second phase and the third phase of the first quadrature clock using a second summing network; outputting a third phase of the second quadrature clock in accordance with an equal sum of the third phase and the fourth phase of the first quadrature clock using a third summing network; and outputting a fourth phase of the second quadrature clock in accordance with an equal sum of the fourth phase and the first phase of the first quadrature clock using a fourth summing network.

A circuit includes a RC-CR circuit and a second circuit. The RC-CR circuit outputs a first signal at a first output node over a RC path, and a second signal at a second output node over a CR path. The second circuit is coupled to the RC-CR circuit at the first output node over the RC path. The second circuit includes an array of capacitors coupled in parallel and a plurality of switches, and each of the array of capacitors is connected, in series, to a corresponding switch in the plurality of switches. Each of the array of capacitors and its corresponding switch are coupled between the first output node and a ground. The plurality of switches is switched on or off such that the first signal and the second signal have a phase difference that falls within a predetermined phase range.

A circuit and a method for automatically calibrating a phase interpolator are provided. Phase information of a reference clock signal and an output clock signal are processed by a phase detector to detect a phase difference of the two clock signals. A difference value between the phase difference and a standard phase difference corresponding to the digital control code is obtained, to generate compensation information. The compensation information is sent to the phase interpolator control unit for storage. When the phase interpolator operates normally, a phase interpolator control unit generates a control signal based on the compensation information, to regulate the phase value of the output clock signal of the phase interpolator.