A variable gain amplifier includes a first transconductor circuit coupled to a first input terminal, a first output terminal, and a second output terminal of the variable gain amplifier, the first transconductor circuit including: a plurality of positive coefficient transistors coupled to the first output terminal and configured to selectively conduct current in response to a first binary code, a plurality of negative coefficient transistors coupled to the second output terminal and configured to selectively conduct current in response to a second binary code, and a plurality of amplifying transistors, each having a gate electrode coupled to the first input terminal, a first electrode coupled to a ground reference, and a second electrode coupled to a pair of coefficient transistors including one of the plurality of positive coefficient transistors and one of the plurality of negative coefficient transistors.

A compensation signal generator generates a compensation signal for canceling an electromagnetic noise on a connection line on the basis of a detection signal of a noise detector. A compensation signal injector injects the compensation signal into the connection line. A compensation signal detector outputs a detection signal of the compensation signal. A low-frequency component subtraction unit amplifies a component in a predetermined first frequency region of the detection signal and negatively feeds back the amplified component to the compensation signal generator. An intermediate frequency component addition unit positively feeds back a component of a predetermined second frequency that is higher than the first frequency region in the detection signal to the compensation signal generator.

There is provided an optical encoder including a phase shifter circuit, two multiplexers, two digital circuits and four comparators. The phase shifter circuit receives signals from an amplifier and outputs multiple phase shifted signals. Each of the two multiplexers receives a half of the multiple phase shifted signals and outputs two pairs of phase shifted signals, each pair having 180 degrees phase difference, respectively to two comparators connected thereto. Each of the two digital circuits controls the corresponding multiplexer to select the two pairs of phase shifted signals from the half of the multiple phase shifted signals.

A communication circuit is disclosed. The communication circuit includes a clock input, and a clock divider configured to generate an output clock signal having a fundamental frequency which is substantially equal to a fundamental frequency of an input clock signal received at the clock input divided by a factor of (2N+1)/2N, where the clock divider is configured to generate 2N+1 pre-aligned phase shifted clock signals based at least in part on the input clock signal, generate 2N unique phase shifted clock signals based at least in part on the 2N+1 pre-aligned phase shifted clock signals, where the 2N unique phase shifted clock signals are substantially separated in phase by 360/2N degrees, and generate the output clock signal based at least in part on the 2N unique phase shifted clock signals, and a mixer, configured to receive the output clock signal.

A device for wireless communications can include a phase selector, a coarse delay line, and a digitally controlled edge interpolator (DCEI). The phase selector receives an input signal and is coupled to the coarse delay line. The coarse delay line can provide one of a plurality of delay ranges. A DCEI, connected to the coarse delay line can provide a fine delay output signal.

A shift register generates a synthesized pulse having a different pulse width according to which one of a first phase pulse and a second phase pulse is inputted, generates an internal shifted synthesized pulse and a shifted synthesized pulse from the synthesized pulse, and generates a detection signal by detecting a pulse width of the internal shifted synthesized pulse. The shift register outputs the shifted synthesized pulse as one of a first shifted phase pulse and a second shifted phase pulse based on the detection signal.

There is provided an optical encoder including a phase shifter circuit, two multiplexers, two digital circuits and four comparators. The phase shifter circuit receives signals from an amplifier and outputs multiple phase shifted signals. Each of the two multiplexers receives a half of the multiple phase shifted signals and outputs two pairs of phase shifted signals, each pair having 180 degrees phase difference, respectively to two comparators connected thereto. Each of the two digital circuits controls the corresponding multiplexer to select the two pairs of phase shifted signals from the half of the multiple phase shifted signals.

Methods and systems are disclosed for clock delay compensation in a multiple chiplet system. Techniques disclosed include distributing, by a clock generator, a clock signal across distribution trees of respective chiplets; measuring phases, by phase detectors, where each phase measurement is associated with a chiplet of the chiplets and is indicative of a propagation speed of the clock signal through the distribution tree of the chiplet. Then, for each chiplet, techniques are further disclosed that determine, by a microcontroller, based on the phase measurements associated with the chiplet, a delay offset, and that delay, based on the delay offset, the propagation of the clock signal through the distribution tree of the chiplet using a delay unit associated with the chiplet.

Devices and methods for implementing an RF integrated circuit device operatively configured to provide the function of RF power splitter with programmable output phase shift are described. Configurable and adjustable phase shift units for use in such IC device are also described.

This application discloses an alternating-current energy detection apparatus, in which a voltage detection unit forms a coupling capacitance together with a tested cable, obtains a first voltage based on an actual voltage and the coupling capacitance, and outputs the first voltage to a data processing unit; a current detection unit detects a tested-cable current, and outputs the tested-cable current to the data processing unit; and the data processing unit receives the first voltage and the tested-cable current, and determines a first voltage value and a tested-cable current value; calculates a product of the first voltage value and a quantity of amplification times of a tested-cable voltage, and determines a tested-cable voltage value; and calculates, based on the tested-cable voltage value and the tested-cable current value, electric energy transmitted by the tested cable.