A semiconductor device includes: a data sampler configured to receive a data signal having a first frequency and to sample the data signal with a clock signal having a second frequency, higher than the first frequency, to output data for a time corresponding to a unit interval of the data signal; an error sampler configured to sample the data signal with an error clock signal having the second frequency and a phase, different from a phase of the clock signal, to output a plurality of pieces of error data for the time corresponding to the unit interval; and an eye-opening monitor (EOM) circuit configured to compare the data with each of the plurality of pieces of error data to obtain an eye diagram of the data signal in the unit interval.

A detection circuit is configured to detect phase information between two clock signals of different frequencies, and the two clock signals include a low frequency clock signal and a high frequency clock signal. The detection circuit includes: a signal generation module, configured to detect the low frequency clock signal at an edge of the high frequency clock signal to generate a to-be-sampled signal, and generate a target sampling signal when the high frequency clock signal is kept at a preset level and the low frequency clock signal meets a preset condition; and a sampling module, connected with the signal generation module and configured to detect the to-be-sampled signal at an edge of the target sampling signal to generate a detection result signal.

The invention provides a method and system for precisely measuring AC power and detecting load impedance using a precise analog front-end, zero-crossing detectors, and a phase detection system capable of extracting precise phase information from the sensed voltage and current measurements. More particularly, the invention provides an apparatus, comprising a transmit circuit configured to generate a wireless field via an antenna for transferring charging power to a receiver device, for determining a phase difference between a first signal and a second signal. The apparatus further comprises a phase detection circuit to output a phase signal indicating a duration of a phase offset between a time-varying voltage and a time-varying current of the transmit circuit. The apparatus further comprises a capacitor configured to receive a variable current from a current source for the duration of the phase offset between the time-varying voltage and a time-varying current.

The techniques of this disclosure may digitally generate a driver signal with a period (or frequency) at a finer resolution than can be achieved by simply counting clock cycles of a system clock. The driver signal may be configured to trigger based on single output clock signal that may be phase-shifted relative to the master system clock. A clock phase shift circuit may increment the phase shift of the output clock signal to any fraction relative to the master system clock. A driver signal generated based on the phase-shifted output clock may achieve the high resolution in frequency desirable when controlling some pulse-width modulated circuits, such as an LLC converter.

An important component in digital circuits is a phase rotator, which permits precise time-shifting (or equivalently, phase rotation) of a clock signal within a clock period. A digital phase rotator can access multiple discrete values of phase under digital control. Such a device can have application in digital clock synchronization circuits, and can also be used for a digital phase modulator that encodes a digital signal. A digital phase rotator has been implemented in superconducting integrated circuit technology, using rapid single-flux-quantum logic (RSFQ). This circuit can exhibit positive or negative phase shifts of a multi-phase clock. Arbitrary precision can be obtained by cascading a plurality of phase rotator stages. Such a circuit forms a phase-modulator that is the core of a direct digital synthesizer that can operate at multi-gigahertz radio frequencies.

Differential clock phase imbalance can produce undesirable spurious content at a digital to analog converter output, or interleaving spurs on an analog-to-digital converter output spectrum, or more generally, in interleaving circuit architectures that depend on rising and falling edges of a differential input clock for triggering digital-to-analog conversion or analog-to-digital conversion. A differential phase adjustment approach measures for the phase imbalance and corrects the differential clock input signals used for generating clock signals which drive the digital-to-analog converter or the analog-to-digital converter. The approach can reduce or eliminate this phase imbalance, thereby reducing detrimental effects due to phase imbalance or differential clock skew.

A phase shift circuitry includes: a signal generation circuitry that receives an input signal, and outputs four signals different in phase from each other by 90 degrees based on the input signal, the four signals includes a first signal and a second signal; four variable amplifier circuitry that each includes a transistor, and amplify the four signals individually, with amplification factors based on control voltages supplied to gates of the transistors, the four variable amplifier circuitry include a first amplifier amplifies the first signal by a first control voltage and a second amplifier amplifies the second signal by a second control voltage; a synthetic circuitry that synthesizes output signals of the four variable amplifier circuitry, and outputs a synthesized signal; and a control circuitry supplies voltages, that are equal to or higher than the gate threshold value, to the first amplifier and the second amplifier.

A phase correction circuit includes: a test clock generation unit including a plurality of signal paths and configurable to generate a plurality of test clock signals in response to a plurality of selection signals and a plurality of phase control signals; a detection unit configured to generate a plurality of detection voltages using the plurality of test clock signals; and a control unit configured to generate the plurality of selection signals, detect phase skews of the plurality of signal paths according to the plurality of detection voltages, and generate the plurality of phase control signals for correcting the phase skews.

A phase and frequency control circuit may be provided. The phase and frequency control circuit may include a division circuit configured to generate a plurality of divided signals by dividing an input signal. The phase and frequency control circuit may include a timing control circuit configured to generate a plurality of timing control signals by sampling the plurality of divided signals according to a phase control code and a sampling reference signal.

A circuit includes a RC-CR circuit and a second circuit. The RC-CR circuit outputs a first signal at a first output node over a RC path, and a second signal at a second output node over a CR path. The second circuit is coupled to the RC-CR circuit at the first output node over the RC path. The second circuit includes an array of capacitors coupled in parallel and a plurality of switches, and each of the array of capacitors is connected, in series, to a corresponding switch in the plurality of switches. Each of the array of capacitors and its corresponding switch are coupled between the first output node and a ground. The plurality of switches is switched on or off such that the first signal and the second signal have a phase difference that falls within a predetermined phase range.