A system includes a controller area network (CAN) transceiver. The CAN transceiver includes a wake-up circuit having an attenuator circuit coupled to a CAN bus. The wake-up circuit also includes a common-gate amplifier circuit coupled to the attenuator circuit. The wake-up circuit also includes an offset generation circuit coupled to the common-gate amplifier circuit.

A system includes a controller area network (CAN) transceiver. The CAN transceiver includes a wake-up circuit having an attenuator circuit coupled to a CAN bus. The wake-up circuit also includes a common-gate amplifier circuit coupled to the attenuator circuit. The wake-up circuit also includes an offset generation circuit coupled to the common-gate amplifier circuit.

A circuit controls a dynamic time constant to remove DC offset from a received optical data signal. The circuit has a first capacitor coupled between a first terminal and a second terminal. A first resistance network is coupled between the second terminal and a reference voltage. A control circuit has a first output coupled to a control input of the first resistance network. The control circuit monotonically increases an effective resistance of the first resistance network to increase the dynamic time constant. The first resistance network has a resistor coupled to the second terminal, and a transistor with a first conduction terminal coupled to the resistor, a second conduction terminal coupled to the reference voltage, and a control terminal coupled to the first output of the control circuit. The first capacitor has a variable capacitance. The monotonic increase in the dynamic time constant can be linear or non-linear.

A circuit controls a dynamic time constant to remove DC offset from a received optical data signal. The circuit has a first capacitor coupled between a first terminal and a second terminal. A first resistance network is coupled between the second terminal and a reference voltage. A control circuit has a first output coupled to a control input of the first resistance network. The control circuit monotonically increases an effective resistance of the first resistance network to increase the dynamic time constant. The first resistance network has a resistor coupled to the second terminal, and a transistor with a first conduction terminal coupled to the resistor, a second conduction terminal coupled to the reference voltage, and a control terminal coupled to the first output of the control circuit. The first capacitor has a variable capacitance. The monotonic increase in the dynamic time constant can be linear or non-linear.

Techniques for autozero to an offset value for a slope detector for voltage droop monitoring are described herein. An aspect includes generating a first offset voltage by a circuit. Another aspect includes generating a second offset voltage by the circuit, the second offset voltage being distinct from the first offset voltage. Another aspect includes, based on a first comparator of the circuit entering an autozero mode, connecting a first terminal of the first comparator to the first offset voltage. Another aspect includes connecting a second terminal of the first comparator to the second offset voltage. Yet another aspect includes performing an autozero operation in the first comparator, wherein a trip point of the first comparator is set to a difference between the first offset voltage and the second offset voltage by the autozero operation.

Techniques for autozero to an offset value for a slope detector for voltage droop monitoring are described herein. An aspect includes generating a first offset voltage by a circuit. Another aspect includes generating a second offset voltage by the circuit, the second offset voltage being distinct from the first offset voltage. Another aspect includes, based on a first comparator of the circuit entering an autozero mode, connecting a first terminal of the first comparator to the first offset voltage. Another aspect includes connecting a second terminal of the first comparator to the second offset voltage. Yet another aspect includes performing an autozero operation in the first comparator, wherein a trip point of the first comparator is set to a difference between the first offset voltage and the second offset voltage by the autozero operation.

A decision feedback equalizer includes: a comparison circuit; a latch circuit configured to latch a result of comparison by the comparison circuit; a setting circuit configured to set a decision threshold of the comparison circuit in accordance with a control signal; and a switch circuit configured to be controlled to be turned on and off by an output signal from the latch circuit, wherein the setting circuit is configured to be connected in parallel with an input stage of the comparison circuit through the switch circuit and operate in synchronization with a clock signal for driving the comparison circuit.

A decision feedback equalizer includes: a comparison circuit; a latch circuit configured to latch a result of comparison by the comparison circuit; a setting circuit configured to set a decision threshold of the comparison circuit in accordance with a control signal; and a switch circuit configured to be controlled to be turned on and off by an output signal from the latch circuit, wherein the setting circuit is configured to be connected in parallel with an input stage of the comparison circuit through the switch circuit and operate in synchronization with a clock signal for driving the comparison circuit.

Various implementations described herein refer to an integrated circuit having a first stage and a second stage. The first stage has first transistors arranged as a diode, a first latch and feedback assist to facilitate shifting an input voltage in a first voltage domain to an output voltage in a second voltage domain. The first stage uses the diode and the first latch to reduce contention between the first latch and input transistors. The diode, the first latch and the feedback assist enable activation of the input transistors with the input voltage. The second stage has second transistors arranged as a second latch followed by output buffers that provide a buffered output voltage as feedback to the feedback assist of the first stage.

Various implementations described herein refer to an integrated circuit having a first stage and a second stage. The first stage has first transistors arranged as a diode, a first latch and feedback assist to facilitate shifting an input voltage in a first voltage domain to an output voltage in a second voltage domain. The first stage uses the diode and the first latch to reduce contention between the first latch and input transistors. The diode, the first latch and the feedback assist enable activation of the input transistors with the input voltage. The second stage has second transistors arranged as a second latch followed by output buffers that provide a buffered output voltage as feedback to the feedback assist of the first stage.