To provide a comparison circuit capable of removing the influence of an offset voltage of a comparator in the comparison circuit and obtaining a highly accurate comparison determination result even at a high temperature. A comparison circuit is equipped with a comparator including a first input terminal inputted with a first input voltage through a first capacitor and inputted with a third input voltage through a third capacitor, a second input terminal inputted with a second input voltage through a second capacitor and inputted with a fourth input voltage through a fourth capacitor, and an output terminal; a first switch which has one end connected to the first input terminal and is turned ON in a sample phase to switch the voltage of the first input terminal to a voltage of the output terminal; and a second switch which has one end connected to the second input terminal and is turned ON in the sample phase to switch the voltage of the second input terminal to a reference voltage.

To provide a comparison circuit capable of removing the influence of an offset voltage of a comparator in the comparison circuit and obtaining a highly accurate comparison determination result even at a high temperature. A comparison circuit is equipped with a comparator including a first input terminal inputted with a first input voltage through a first capacitor and inputted with a third input voltage through a third capacitor, a second input terminal inputted with a second input voltage through a second capacitor and inputted with a fourth input voltage through a fourth capacitor, and an output terminal; a first switch which has one end connected to the first input terminal and is turned ON in a sample phase to switch the voltage of the first input terminal to a voltage of the output terminal; and a second switch which has one end connected to the second input terminal and is turned ON in the sample phase to switch the voltage of the second input terminal to a reference voltage.

A ramp generator includes a current generator, a current mirror, and a first capacitor. The current generator has an input for receiving a clock signal, and an output for providing a current proportional to a frequency of the clock signal using a first transistor having first and second current electrodes and a control electrode, an amplifier that establishes a reference voltage on the second current electrode of the first transistor, and a variable resistor coupled between the second current electrode of the second transistor and ground whose resistance is set according to the frequency of the clock signal. The current mirror has an input coupled to the first terminal of the first transistor, and a second terminal. The first capacitor has a first terminal coupled to the output of the current mirror and providing a ramp signal, and a second terminal coupled to the first power supply voltage terminal.

A ramp generator includes a current generator, a current mirror, and a first capacitor. The current generator has an input for receiving a clock signal, and an output for providing a current proportional to a frequency of the clock signal using a first transistor having first and second current electrodes and a control electrode, an amplifier that establishes a reference voltage on the second current electrode of the first transistor, and a variable resistor coupled between the second current electrode of the second transistor and ground whose resistance is set according to the frequency of the clock signal. The current mirror has an input coupled to the first terminal of the first transistor, and a second terminal. The first capacitor has a first terminal coupled to the output of the current mirror and providing a ramp signal, and a second terminal coupled to the first power supply voltage terminal.

A receiver includes a differential signal generator receiving a single-ended signal, and generating differential signals having a positive signal and a negative signal based on the single-ended signal, a reference signal, and a pair of compensation signals, a pair of charging circuits charging first and second nodes to a power level in a logic low period of a clock signal, a pair of discharging circuits discharging the first and second nodes according to a level of the positive signal and a level of the negative signal, respectively, in a logic high period of the clock signal, a comparator comparing signal levels of the first and second nodes and outputting an offset detection signal of the differential signals, and an offset compensator outputting the reference signal and the pair of compensation signals, each adjusted based on the offset detection signal, to the differential signal generator.

A receiver includes a differential signal generator receiving a single-ended signal, and generating differential signals having a positive signal and a negative signal based on the single-ended signal, a reference signal, and a pair of compensation signals, a pair of charging circuits charging first and second nodes to a power level in a logic low period of a clock signal, a pair of discharging circuits discharging the first and second nodes according to a level of the positive signal and a level of the negative signal, respectively, in a logic high period of the clock signal, a comparator comparing signal levels of the first and second nodes and outputting an offset detection signal of the differential signals, and an offset compensator outputting the reference signal and the pair of compensation signals, each adjusted based on the offset detection signal, to the differential signal generator.

A deskew circuit for a differential signal is provided. A first common mode voltage generating circuit generates a first common mode voltage signal according to first and second differential input signals. A voltage buffer circuit is coupled to the first common mode voltage generating circuit and has an input impedance higher than a preset value, and buffers the first common mode voltage signal and the first and second differential input signals to generate a second common mode voltage signal, a third differential input signal, and a fourth differential input signal. A second common mode voltage generating circuit is coupled to the voltage buffer circuit and generates a third common mode voltage signal according to the third and fourth differential input signals. An output circuit generates a deskew output signal according to the third and fourth differential input signals and the second and third common mode voltage signals.

A deskew circuit for a differential signal is provided. A first common mode voltage generating circuit generates a first common mode voltage signal according to first and second differential input signals. A voltage buffer circuit is coupled to the first common mode voltage generating circuit and has an input impedance higher than a preset value, and buffers the first common mode voltage signal and the first and second differential input signals to generate a second common mode voltage signal, a third differential input signal, and a fourth differential input signal. A second common mode voltage generating circuit is coupled to the voltage buffer circuit and generates a third common mode voltage signal according to the third and fourth differential input signals. An output circuit generates a deskew output signal according to the third and fourth differential input signals and the second and third common mode voltage signals.

Systems, methods, and devices for voltage identification using a pulse-width modulation signal are provided. Such an integrated circuit device may include an input/output (I/O) interface and voltage identification (VID) circuitry. The VID circuitry may be coupled to the input/output interface. The voltage identification circuitry may generate a voltage identification signal that is output on the input/output interface. The voltage identification signal may include a pulsed signal having a particular duty cycle that corresponds to a specified voltage level to enable a voltage regulator that receives the voltage identification signal to provide an input voltage to the integrated circuit device at the specified voltage level.

Systems, methods, and devices for voltage identification using a pulse-width modulation signal are provided. Such an integrated circuit device may include an input/output (I/O) interface and voltage identification (VID) circuitry. The VID circuitry may be coupled to the input/output interface. The voltage identification circuitry may generate a voltage identification signal that is output on the input/output interface. The voltage identification signal may include a pulsed signal having a particular duty cycle that corresponds to a specified voltage level to enable a voltage regulator that receives the voltage identification signal to provide an input voltage to the integrated circuit device at the specified voltage level.